1TnC memory bit-cell having stacked and folded planar capacitors with lateral offset
摘要
說明書
At that point the PL for the desired FE capacitor is toggled, which results into voltage buildup on the SNx node. The voltage build-up on the SNx node may be different voltage levels depending upon whether the FE capacitor state was logic 0 or logic 1. The time-sampling of this voltage relative to a reference expected value, results in detection of the state in which the FE capacitor was programmed. After reading the value, a write-back operation can be done to get the value restored to the FE capacitor, as reads are destructive read in this configuration, in accordance with some embodiments.
In the write back process, the selected bit-cell BL (e.g., BLx) is charged to Vdd or set to 0V depending upon whether a logic 1 or a logic 0 is written back to the selected bit-cell. The value written back to the bit-cell is the same value that the sense amplifier detects when reading the voltage on the BL. The write back mechanism is like the write operation described with reference to
While various embodiments are described with reference to select transistors as being n-type transistors, the n-type transistors may be replaced with p-type transistors. In one such case, the logic associated with the transistors may be modified to achieve the correct polarity of the signals for proper function of the bit-cells.
