FIG. 16B illustrates multi-element FE gain bit-cell 1620 with stacked and folded planar capacitors that use extended bottom electrodes and aligned central pedestals, in accordance with some embodiments. Compared to FIG. 16A, here the through vias 1322 are used for storage node sn1 to connect to various extended bottom electrodes of different layers. Vias 1322 are also referred to as pedestals as they connect one metal layer to another metal layer (e.g., extended bottom electrode 1301 of M2 layer to extended bottom electrode 1301 of M4 layer). Via 1322 is connected to extended bottom electrode 1301 and to subsequent via 1323. In various embodiments, vias 1322 and 1323 are vertically aligned. This embodiment allows for simpler fabrication compared to 1TnC bit-cell 1300 because fewer vias for storage node sn1 are used and those vias are aligned to form through vias. In some embodiments, vias 1322 and 1323 are formed using the same technology which is used to form through-silicon vias (TSVs).
