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1TnC memory bit-cell having stacked and folded planar capacitors with lateral offset

專利號(hào)
US11997853B1
公開日期
2024-05-28
申請(qǐng)人
Kepler Computing Inc.（US CA San Francisco）
發(fā)明人
Rajeev Kumar Dokania; Amrita Mathuriya; Debo Olaosebikan; Tanay Gosavi; Noriyuki Sato; Sasikanth Manipatruni
IPC分類
H10B53/30
技術(shù)領(lǐng)域
capacitors,capacitor,bit,in,electrode,node,layer,some,memory,wherein
地域： CA CA San Francisco

摘要

A configuration for efficiently placing a group of capacitors with one terminal connected to a common node is described. The capacitors are stacked and folded along the common node. In a stack and fold configuration, devices are stacked vertically (directly or with a horizontal offset) with one terminal of the devices being shared to a common node, and further the capacitors are placed along both sides of the common node. The common node is a point of fold. In one example, the devices are capacitors. N number of capacitors can be divided in L number of stack layers such that there are N/L capacitors in each stacked layer. The N/L capacitors are shorted together with an electrode (e.g., bottom electrode). The electrode can be metal, a conducting oxide, or a combination of a conducting oxide and a barrier material. The capacitors can be planar, non-planar or replaced by memory elements.

說(shuō)明書

‘a(chǎn)’ ‘b’ ‘c’ Second control (down) Threshold 0 0 0 1 (enable MN1) 2 1 0 0 1 (enable MN1) 3 1 1 0 1 (enable MN1) 3 1 1 1 1 (enable MN1) 3

In the evaluation phase, 3-input capacitive circuit 1820 can then behave as a majority/majority gate (when threshold is 2) or an AND/NAND gate (when threshold is 3). Note, this example assumes equal weights for C1, C2, and C3 (e.g., C1=C2=C3). In some embodiments, the threshold may change (e.g., from 3 to 2 or to 1) when the ratio of capacitances of capacitors C1, C2, and/or C3 are modified.

Table 4 illustrates that when inputs ‘a(chǎn)’, ‘b’, and ‘c’ are conditioned and pull-down device MN1 is enabled during the reset phase, then the threshold is set to 2, 3, or 4. When the capacitors comprise paraelectric material, different thresholds are achieved compared to the linear dielectric material for the same input conditioning. Table 4 is the case when capacitors comprise paraelectric material.

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