白丝美女被狂躁免费视频网站,500av导航大全精品,yw.193.cnc爆乳尤物未满,97se亚洲综合色区,аⅴ天堂中文在线网官网

1TnC memory bit-cell having stacked and folded planar capacitors with lateral offset

專(zhuān)利號(hào)
US11997853B1
公開(kāi)日期
2024-05-28
申請(qǐng)人
Kepler Computing Inc.(US CA San Francisco)
發(fā)明人
Rajeev Kumar Dokania; Amrita Mathuriya; Debo Olaosebikan; Tanay Gosavi; Noriyuki Sato; Sasikanth Manipatruni
IPC分類(lèi)
H10B53/30
技術(shù)領(lǐng)域
capacitors,capacitor,bit,in,electrode,node,layer,some,memory,wherein
地域: CA CA San Francisco

摘要

A configuration for efficiently placing a group of capacitors with one terminal connected to a common node is described. The capacitors are stacked and folded along the common node. In a stack and fold configuration, devices are stacked vertically (directly or with a horizontal offset) with one terminal of the devices being shared to a common node, and further the capacitors are placed along both sides of the common node. The common node is a point of fold. In one example, the devices are capacitors. N number of capacitors can be divided in L number of stack layers such that there are N/L capacitors in each stacked layer. The N/L capacitors are shorted together with an electrode (e.g., bottom electrode). The electrode can be metal, a conducting oxide, or a combination of a conducting oxide and a barrier material. The capacitors can be planar, non-planar or replaced by memory elements.

說(shuō)明書(shū)

FIG. 18E illustrates 3-input configurable threshold gate 1850 (e.g., 1800) with pull-down device and having linear or paraelectric capacitors that are arranged as stacked and folded planar capacitors, and with aligned central pedestal, and an extended metal layer, in accordance with some embodiments. 3-input configurable threshold gate 1850 is like 3-input configurable threshold gate 1840 but with extended shared metal 1851 instead of extended bottom electrode 1831. While extended shared metal 1851 is coupled to the bottom electrodes of each capacitor in the same horizontal region, each capacitor includes its own bottom electrode. In various embodiments, the vias or pedestals 1852 and 1853 for summing node n1 are coupled or connected to extended shared metal 1851.

In some embodiments, pedestals or vias are formed for both the top and bottom electrodes of the planar capacitors. In this embodiment, the height of the stacked capacitors is raised, and the fabrication process adds an additional step of forming a top pedestal or via which contacts with respective plate-line electrodes.

權(quán)利要求

1
微信群二維碼
意見(jiàn)反饋