FIG. 18F illustrates 3-input configurable threshold gate 1860 with the pull-down device and having linear or paraelectric capacitors that are arranged as stacked and folded non-planar capacitors, and with an aligned central pedestal and an extended metal layer, in accordance with some embodiments. In this example three capacitors are stacked and folded. In some embodiments, at least two columns of shared metal are connected to summing node n1 1863. For further folding of capacitors, additional columns of shared metal can be connected to summing node n1 1863. In one such embodiment, via1 for n1 is made wider to accommodate connection with additional columns. In some embodiments, all three capacitors are directly coupled to summing node n1 1863 and there are no capacitors vertically over the capacitors. In some embodiments, at least two capacitors are on a vertical stack and one capacitor is on a separate stack directly coupled to summing node n1 1863.
In some embodiments, summing node n1 1863 is coupled to a metal stub on M1 which in turn is coupled to a source contact of transistor MN1. The drain contact of transistor MN1 is connected to Vss (ground). The gate terminal of the transistor is connected to control node “down”. The columns of vertical metal form the bottom electrodes of the capacitors or are directly adjacent to the bottom electrodes of the capacitors.
