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1TnC memory bit-cell having stacked and folded planar capacitors with lateral offset

專利號(hào)
US11997853B1
公開日期
2024-05-28
申請人
Kepler Computing Inc.（US CA San Francisco）
發(fā)明人
Rajeev Kumar Dokania; Amrita Mathuriya; Debo Olaosebikan; Tanay Gosavi; Noriyuki Sato; Sasikanth Manipatruni
IPC分類
H10B53/30
技術(shù)領(lǐng)域
capacitors,capacitor,bit,in,electrode,node,layer,some,memory,wherein
地域： CA CA San Francisco

摘要

A configuration for efficiently placing a group of capacitors with one terminal connected to a common node is described. The capacitors are stacked and folded along the common node. In a stack and fold configuration, devices are stacked vertically (directly or with a horizontal offset) with one terminal of the devices being shared to a common node, and further the capacitors are placed along both sides of the common node. The common node is a point of fold. In one example, the devices are capacitors. N number of capacitors can be divided in L number of stack layers such that there are N/L capacitors in each stacked layer. The N/L capacitors are shorted together with an electrode (e.g., bottom electrode). The electrode can be metal, a conducting oxide, or a combination of a conducting oxide and a barrier material. The capacitors can be planar, non-planar or replaced by memory elements.

說明書

0 (enable MP1) 1 1 1 1 0 0 0 (enable MP1) 2 1 1 1 1 0 0 (enable MP1) 2 1 1 1 1 1 0 (enable MP1) 3

In the evaluation phase, 5-input capacitive circuit 1900 can then behave as an always-on circuit that drives a constant logic value on node n1 (when threshold is 0), an OR/NOR gate (when threshold is 1), a majority-0/minority-0 gate or a threshold gate (when threshold is 2), or a majority/minority gate (when threshold is 3). Note, this example assumes equal weights for C1, C2, C3, C4, and C5 (e.g., C1=C2=C3=C4=C5). In some embodiments, the threshold may change (e.g., from 1 to 2 or to 3, 4, or 5 or any other value) when the ratio of capacitances of capacitors C1, C2, C3, C4, and/or C5 are modified.

In some embodiments, by turning on/off the pull-up device MP1 and pull-down device MN1 in a sequence, and conditioning the inputs ‘a(chǎn)’, ‘b’, ‘c’, ‘d’, and ‘e’ during a reset phase, the charge at node n1 is set. As such, in an evaluation phase when the pull-up and pull-down devices (MP1 and MN1) are disabled, 5-input capacitive circuit 1900 attains a desired function.

權(quán)利要求

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