1TnC memory bit-cell having stacked and folded planar capacitors with lateral offset
摘要
說明書
In some embodiments, the capacitors of 1TnC and the multi-gain element bit-cell include ferroelectric or paraelectric material. While memory with memory bit-cells comprising ferroelectric material provide a new class of non-volatile memories, traditional ferroelectric memories suffer from charge degradation over time, for example, during read operations. Such memories also suffer from charge disturbance when neighboring bit-cells are accessed. Such disturbance may be a function of routing configuration of plate-line(s), relative to bit-lines and word-lines. Further, leakage from transistors coupled to ferroelectric capacitor(s) may further degrade charge on a storage node connected to the capacitor.
Consider the case for an unselected memory bit-cell where word-line to a gate of an n-type transistor of the bit-cell is at logic low. Continuing with this example, when the plate-line coupled to the capacitor is parallel to a bit-line, which is coupled to a source terminal or a drain terminal of the n-type transistor, transitions from logic low to logic high on the plate line results in a field across the ferroelectric capacitor of this unselected memory bit-cell. This field causes polarization decay for a ferroelectric material in the ferroelectric capacitor. The polarization decay causes the charge on the storage node to rise, which in turn weakens the disturb electric field across the ferroelectric material of the unselected bit-cell. The weakened disturb electric field causes the n-type transistor to leak, which in turn causes the disturb field to increase. As such, the unselected bit-cell suffers from charge disturb when the plate-line is parallel to the bit-line. Depending on the charge stored in the ferroelectric capacitor, this disturb field can either disturb or reinforce the stored value in the ferroelectric capacitor.
