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1TnC memory bit-cell having stacked and folded planar capacitors with lateral offset

專利號
US11997853B1
公開日期
2024-05-28
申請人
Kepler Computing Inc.（US CA San Francisco）
發(fā)明人
Rajeev Kumar Dokania; Amrita Mathuriya; Debo Olaosebikan; Tanay Gosavi; Noriyuki Sato; Sasikanth Manipatruni
IPC分類
H10B53/30
技術(shù)領(lǐng)域
capacitors,capacitor,bit,in,electrode,node,layer,some,memory,wherein
地域： CA CA San Francisco

摘要

A configuration for efficiently placing a group of capacitors with one terminal connected to a common node is described. The capacitors are stacked and folded along the common node. In a stack and fold configuration, devices are stacked vertically (directly or with a horizontal offset) with one terminal of the devices being shared to a common node, and further the capacitors are placed along both sides of the common node. The common node is a point of fold. In one example, the devices are capacitors. N number of capacitors can be divided in L number of stack layers such that there are N/L capacitors in each stacked layer. The N/L capacitors are shorted together with an electrode (e.g., bottom electrode). The electrode can be metal, a conducting oxide, or a combination of a conducting oxide and a barrier material. The capacitors can be planar, non-planar or replaced by memory elements.

說明書

Since the voltage on node n1 for the various threshold gates described herein is closer to rail-to-rail voltage compared to the case when linear input capacitors are used, subsequent driver circuitry 1901 can be removed. As such, the input capacitors with nonlinear polar material can drive another capacitive input circuit directly. Here, closer to rail-to-rail voltage on node n1 using nonlinear polar material based capacitors (e.g., ferroelectric or paraelectric capacitors) implies that the static leakage in the subsequent driver 1901 is reduced compared to the case when voltage on n1 is not close to rail-to-rail voltage. When linear capacitors are used, a voltage divider is formed on node n1 based on the number of capacitors and their logic inputs. Such a voltage divider results in non-rail-to-rail voltage on node n1 that results in static leakage in the subsequent driver 1901. When nonlinear capacitors are used, the voltage divider is not a linear voltage divider. This results in a much closer rail-to-rail voltage on n1 which reduces static leakage in the subsequent driver 1901. The higher the nonlinearity, the closer the voltage on node n1 is rail-to-rail. Nonlinear capacitors as shown in various embodiments allow the logic gate to have more inputs compared to the case when linear capacitors are used while keeping the leakage through driver 1901 low.

In various embodiments, 5-input configurable threshold gate 1900 can be configured as a stack and fold configuration as described with reference to FIGS. 18A-G. For linear non-planar capacitors, example structures are described with reference to FIGS. 3A-B. For non-linear non-planar capacitors, example structures are described with reference to FIGS. 5A-B.

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