FIG. 19B illustrates 5-input configurable threshold gate 1920 (e.g., 1900) with the pull-down device MN1 and pull-up device MN2 and with ferroelectric capacitors that are arranged as stacked and folded planar capacitors, and with an aligned central pedestal and extended bottom electrode, in accordance with some embodiments. In some embodiments, the five capacitors C1, C2, C3, C4, and C5 are arranged in a stacked and folded configuration, where there are 3 stacks and one fold along point of fold 1927. In some embodiments, a vertical tower of vias and metal layers are used to extend the summing node n1 to higher levels along the vertical direction. For example, via 1922 is connected to shared bottom electrode 1301 and to summing node n1 on M2. One or more vias 1923 then couple summing node n1 on M2 to the next shared bottom electrode on M4, and so on. As such, a network of vias is used to connect summing node n1 on M1 to shared bottom electrodes of each capacitive structure on various metal layers.
In some embodiments, the first stack capacitors C1 and C2 are symmetrically placed on either side of the point of fold 1327. In some embodiments, the second stack capacitors C3 and C4 are symmetrically placed on either side of the point of fold 1327. On the third stack, capacitor C5 can be placed above capacitor C3 such that there is no horizontal offset between capacitor C3 and C5, in accordance with some embodiments. In this example, the third stack is asymmetric because there is one capacitor on one side of point of fold 1327 and no capacitor on the other side of point of fold 1327. In some embodiments, the capacitors are horizontally offset relative to their bottom capacitors.
