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1TnC memory bit-cell having stacked and folded planar capacitors with lateral offset

專利號
US11997853B1
公開日期
2024-05-28
申請人
Kepler Computing Inc.（US CA San Francisco）
發(fā)明人
Rajeev Kumar Dokania; Amrita Mathuriya; Debo Olaosebikan; Tanay Gosavi; Noriyuki Sato; Sasikanth Manipatruni
IPC分類
H10B53/30
技術(shù)領(lǐng)域
capacitors,capacitor,bit,in,electrode,node,layer,some,memory,wherein
地域： CA CA San Francisco

摘要

A configuration for efficiently placing a group of capacitors with one terminal connected to a common node is described. The capacitors are stacked and folded along the common node. In a stack and fold configuration, devices are stacked vertically (directly or with a horizontal offset) with one terminal of the devices being shared to a common node, and further the capacitors are placed along both sides of the common node. The common node is a point of fold. In one example, the devices are capacitors. N number of capacitors can be divided in L number of stack layers such that there are N/L capacitors in each stacked layer. The N/L capacitors are shorted together with an electrode (e.g., bottom electrode). The electrode can be metal, a conducting oxide, or a combination of a conducting oxide and a barrier material. The capacitors can be planar, non-planar or replaced by memory elements.

說明書

The embodiments of the disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure, which, however, should not be taken to limit the disclosure to the specific embodiments, but are for explanation and understanding only.

FIG. 1 illustrates a set of plots that show behavior of a ferroelectric capacitor, a paraelectric capacitor, and a linear capacitor.

FIG. 2 illustrates a planar linear capacitor structure, in accordance with some embodiments.

FIG. 3A illustrates a non-planar linear capacitor structure, in accordance with some embodiments.

FIG. 3B illustrates a non-planar linear capacitor structure without conductive oxides, in accordance with some embodiments.

FIG. 4A illustrates a planar ferroelectric or paraelectric capacitor structure, in accordance with some embodiments.

FIG. 4B illustrates three planar ferroelectric or paraelectric capacitor structures, respectively, in accordance with some embodiments.

FIG. 4C illustrates a pedestal that connects to the top and/or bottom electrodes of the planar ferroelectric or paraelectric capacitor.

FIG. 5A illustrates a non-planar ferroelectric or paraelectric capacitor structure, in accordance with some embodiments.

權(quán)利要求

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