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1TnC memory bit-cell having stacked and folded planar capacitors with lateral offset

專利號
US11997853B1
公開日期
2024-05-28
申請人
Kepler Computing Inc.（US CA San Francisco）
發(fā)明人
Rajeev Kumar Dokania; Amrita Mathuriya; Debo Olaosebikan; Tanay Gosavi; Noriyuki Sato; Sasikanth Manipatruni
IPC分類
H10B53/30
技術(shù)領(lǐng)域
capacitors,capacitor,bit,in,electrode,node,layer,some,memory,wherein
地域： CA CA San Francisco

摘要

A configuration for efficiently placing a group of capacitors with one terminal connected to a common node is described. The capacitors are stacked and folded along the common node. In a stack and fold configuration, devices are stacked vertically (directly or with a horizontal offset) with one terminal of the devices being shared to a common node, and further the capacitors are placed along both sides of the common node. The common node is a point of fold. In one example, the devices are capacitors. N number of capacitors can be divided in L number of stack layers such that there are N/L capacitors in each stacked layer. The N/L capacitors are shorted together with an electrode (e.g., bottom electrode). The electrode can be metal, a conducting oxide, or a combination of a conducting oxide and a barrier material. The capacitors can be planar, non-planar or replaced by memory elements.

說明書

In some embodiments, in the first row, the second terminal of ME0,1 is coupled to plate-line PL0_1, the second terminal of ME0,2 is coupled to plate-line PL0_2, the second terminal of ME0,3 is coupled to plate-line PL0_3, and the second terminal of ME0,4 is coupled to plate-line PL0_4. In some embodiments, in the second row, the second terminal of ME1,1 is coupled to plate-line PL0_5, the second terminal of ME1,2 is coupled to plate-line PL0_6, the second terminal of ME1,3 is coupled to plate-line PL0_7, and the second terminal of ME1,4 is coupled to plate-line PL0_8. In some embodiments, in the third row, the second terminal of ME2,1 is coupled to plate-line PL0_9, the second terminal of ME2,2 is coupled to plate-line PL0_10, the second terminal of ME2,3 is coupled to plate-line PL0_11, and the second terminal of ME2,4 is coupled to plate-line PL0_12. In some embodiments, in the fourth row, the second terminal of ME3,1 is coupled to plate-line PL0_13, the second terminal of ME3,2 is coupled to plate-line PL0_14, the second terminal of ME3,3 is coupled to plate-line PL0_15, and the second terminal of ME3,4 is coupled to plate-line PL0_16.

權(quán)利要求

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