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1TnC memory bit-cell having stacked and folded planar capacitors with lateral offset

專利號
US11997853B1
公開日期
2024-05-28
申請人
Kepler Computing Inc.（US CA San Francisco）
發(fā)明人
Rajeev Kumar Dokania; Amrita Mathuriya; Debo Olaosebikan; Tanay Gosavi; Noriyuki Sato; Sasikanth Manipatruni
IPC分類
H10B53/30
技術領域
capacitors,capacitor,bit,in,electrode,node,layer,some,memory,wherein
地域： CA CA San Francisco

摘要

A configuration for efficiently placing a group of capacitors with one terminal connected to a common node is described. The capacitors are stacked and folded along the common node. In a stack and fold configuration, devices are stacked vertically (directly or with a horizontal offset) with one terminal of the devices being shared to a common node, and further the capacitors are placed along both sides of the common node. The common node is a point of fold. In one example, the devices are capacitors. N number of capacitors can be divided in L number of stack layers such that there are N/L capacitors in each stacked layer. The N/L capacitors are shorted together with an electrode (e.g., bottom electrode). The electrode can be metal, a conducting oxide, or a combination of a conducting oxide and a barrier material. The capacitors can be planar, non-planar or replaced by memory elements.

說明書

In various embodiments, the staggered memory elements on shared bottom electrode 1301 or shared metal 1401 allow for metal route escapes for the plate-lines. For example, ME0,7 is coupled to plate-line PL1_7, ME0,3 is coupled to plate-line PL0_3, ME0,8 is coupled to plate-line PL1_8, ME0,4 is coupled to plate-line PL0_4. In some embodiments, these plate-lines are parallel to one another. The staggered configuration allows for the plate-line escapes on either side of shared bottom electrode 1301 or shared metal 1401, in accordance with some embodiments. In some embodiments, all memory elements of the 1TnME bit-cell are placed in a staggered configuration of FIG. 20C on shared bottom electrode 1301 or shared metal 1401. In one such embodiment, the memory elements are not stacked and folded, but staggered with horizontal offsets in the x and y directions. In some embodiments, via 1423 is removed when all memory elements are placed in a staggered configuration of FIG. 20C on shared bottom electrode 1301 or shared metal 1401.

權利要求

1
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