1TnC memory bit-cell having stacked and folded planar capacitors with lateral offset
摘要
說(shuō)明書(shū)
Continuing with the example of a ferroelectric based memory bit-cell, the memory bit-cell is coupled to one or more plate-lines, a word-line, and a bit-line. The routing of the plate-line(s) relative to the word-line or the bit-line impacts the performance of the bit-cell. Some embodiments describe a read and write scheme (herein referred to as a pulsing scheme) for memory arrays where plate-line(s) is/are parallel to a bit-line. Some embodiments describe a pulsing scheme for memory arrays where plate-line(s) is/are parallel to a word-line. The pulsing schemes described with reference to various embodiments depend on a structure or configuration of a memory bit-cell. Some embodiments describe a pulsing scheme for a two-transistor, one-capacitor (2T1C) bit-cell configuration. Some embodiments describe a pulsing scheme for a one-transistor, n-capacitors (1TnC) bit-cell configuration. Some embodiments describe a pulsing scheme for multi-element FE gain bit-cell configuration.
