1TnC memory bit-cell having stacked and folded planar capacitors with lateral offset
摘要
說明書
Example 18a: The apparatus of example 17a, wherein the first set of capacitors includes a first capacitor which includes: a first layer coupled to the first conductive electrode, wherein the first layer comprises first metal; a second layer around the first layer, wherein the second layer comprises a first conductive oxide; a third layer comprising a ferroelectric dielectric material, wherein the third layer is around the second layer; a fourth layer around the third layer, wherein the fourth layer comprises a second conductive oxide, wherein the fourth layer is around the third layer; and a fifth layer around the fourth layer, wherein the fifth layer comprises a second metal, wherein a first plate-line is adjacent to part of the fifth layer.
Example 19a: A system comprising: a processor circuitry to execute one or more instructions; a memory circuitry to store the one or more instructions; and a communication interface to allow the processor circuitry to communicate with another device, wherein the memory circuitry includes a plurality of bit-cells organized in a memory array, wherein an individual bit-cell of the plurality of bit-cells includes: a transistor having a gate terminal coupled to a word-line, a source terminal couple to a bit-line, and a drain terminal coupled to a storage node; and a plurality of capacitors having a first terminal coupled to the storage node, wherein a second terminal of an individual capacitor of the plurality of capacitors is coupled to an individual plate-line, wherein the plurality of capacitors are non-planar capacitors that are arranged in a stacked and folded configuration.
