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1TnC memory bit-cell having stacked and folded planar capacitors with lateral offset

專利號
US11997853B1
公開日期
2024-05-28
申請人
Kepler Computing Inc.（US CA San Francisco）
發(fā)明人
Rajeev Kumar Dokania; Amrita Mathuriya; Debo Olaosebikan; Tanay Gosavi; Noriyuki Sato; Sasikanth Manipatruni
IPC分類
H10B53/30
技術(shù)領(lǐng)域
capacitors,capacitor,bit,in,electrode,node,layer,some,memory,wherein
地域： CA CA San Francisco

摘要

A configuration for efficiently placing a group of capacitors with one terminal connected to a common node is described. The capacitors are stacked and folded along the common node. In a stack and fold configuration, devices are stacked vertically (directly or with a horizontal offset) with one terminal of the devices being shared to a common node, and further the capacitors are placed along both sides of the common node. The common node is a point of fold. In one example, the devices are capacitors. N number of capacitors can be divided in L number of stack layers such that there are N/L capacitors in each stacked layer. The N/L capacitors are shorted together with an electrode (e.g., bottom electrode). The electrode can be metal, a conducting oxide, or a combination of a conducting oxide and a barrier material. The capacitors can be planar, non-planar or replaced by memory elements.

說明書

Example 11c: The apparatus of example 9c, wherein the individual capacitor includes: a first layer coupled to the shared bottom electrode which is coupled to the storage node, wherein the first layer comprises a first refractive inter-metallic material, wherein the first layer extends along an x-plane; a second layer on the first layer, wherein the second layer comprises a first conductive oxide, wherein the second layer extends along the x-plane; a third layer comprising non-linear polar material, wherein the third layer is on the second layer, wherein the third layer extends along the x-plane; a fourth layer on the third layer, wherein the fourth layer comprises a second conductive oxide, wherein the fourth layer extends along the x-plane; and a fifth layer on the fourth layer, wherein the fifth layer comprises a second refractive inter-metallic material, wherein the individual plate-line is coupled to the fifth layer through a switch.

Example 13c: The apparatus of example 11c, wherein the individual capacitor includes: a first layer coupled to the shared bottom electrode which is coupled to the storage node, wherein the first layer comprises a first conductive oxide, wherein the first layer extends along an x-plane; a second layer comprising non-linear polar material, wherein the second layer is on the first layer, wherein the second layer extends along the x-plane; and a third layer on the second layer, wherein the third layer comprises a second conductive oxide, wherein the third layer extends along the x-plane, wherein the individual plate-line is coupled to the third layer.

Example 14c: The apparatus of example 1c, wherein the individual plate-line is parallel to the bit-line.

Example 15c: The apparatus of example 1c, wherein the plurality of capacitors comprises non-linear polar material.

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