1TnC memory bit-cell having stacked and folded planar capacitors with lateral offset
摘要
說明書
Example 20d: A system comprising: a processor circuitry to execute one or more instructions; a memory circuitry to store the one or more instructions; and a communication interface to allow the processor circuitry to communicate with another device, wherein the memory circuitry includes a plurality of bit-cells organized in a memory array, wherein an individual bit-cell of the plurality of bit-cells includes an apparatus according to any one of examples 1d to 17d.
Example 1e: An apparatus comprising: a first transistor having a first gate terminal coupled to a word-line, a first source terminal couple to a bit-line, and a first drain terminal coupled to a storage node; a second transistor coupled to the first transistor, wherein the second transistor includes a second gate terminal coupled to the storage node, a second source terminal couple to a sense line, and a second drain terminal coupled to a bias; and a plurality of capacitors having a first terminal coupled to the storage node, wherein a second terminal of an individual capacitor of the plurality of capacitors is coupled to an individual plate-line, wherein the plurality of capacitors are non-planar capacitors that are arranged in a stacked and folded configuration.
Example 2e: The apparatus of example 1e comprising: a first conductive electrode directly connected to the storage node, wherein the first conductive electrode extends vertically away from the storage node; and a second conductive electrode directly connected to the storage node, wherein the second conductive electrode extends vertically away from the storage node, wherein the first conductive electrode and the second conductive electrode are substantially parallel.
