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1TnC memory bit-cell having stacked and folded planar capacitors with lateral offset

專利號
US11997853B1
公開日期
2024-05-28
申請人
Kepler Computing Inc.（US CA San Francisco）
發(fā)明人
Rajeev Kumar Dokania; Amrita Mathuriya; Debo Olaosebikan; Tanay Gosavi; Noriyuki Sato; Sasikanth Manipatruni
IPC分類
H10B53/30
技術(shù)領(lǐng)域
capacitors,capacitor,bit,in,electrode,node,layer,some,memory,wherein
地域： CA CA San Francisco

摘要

A configuration for efficiently placing a group of capacitors with one terminal connected to a common node is described. The capacitors are stacked and folded along the common node. In a stack and fold configuration, devices are stacked vertically (directly or with a horizontal offset) with one terminal of the devices being shared to a common node, and further the capacitors are placed along both sides of the common node. The common node is a point of fold. In one example, the devices are capacitors. N number of capacitors can be divided in L number of stack layers such that there are N/L capacitors in each stacked layer. The N/L capacitors are shorted together with an electrode (e.g., bottom electrode). The electrode can be metal, a conducting oxide, or a combination of a conducting oxide and a barrier material. The capacitors can be planar, non-planar or replaced by memory elements.

說明書

Example 7g: The apparatus of example 4g, wherein the third capacitor includes: a first layer coupled to the second conductive electrode, wherein the first layer comprises a first metal; a second layer around the first layer, wherein the second layer comprises a first conductive oxide; a third layer comprising a ferroelectric dielectric material, wherein the third layer is around the second layer; a fourth layer around the third layer, wherein the fourth layer comprises a second conductive oxide, wherein the fourth layer is around the third layer; and a fifth layer around the fourth layer, wherein the fifth layer comprises a second metal, wherein a second node is adjacent to part of the fifth layer, wherein the second node is coupled to the third input.

Example 8g: The apparatus of example 7g, wherein: the first layer has a first circumference; the second layer has a second circumference; the third layer has a third circumference; the fourth layer has a fourth circumference; and the fifth layer has a fifth circumference, wherein the fifth circumference is larger than the fourth circumference, wherein the fourth circumference is larger than the third circumference, wherein the third circumference is larger than the second circumference, wherein the second circumference is larger than the first circumference.

Example 9g: The apparatus of example 3g, wherein the first conductive electrode or the second conductive electrode comprises metal, a first conducting oxide, or a combination of a second conducting oxide and an insulative material.

Example 10g: The apparatus of example 3g, wherein the first conductive electrode is a first shared bottom electrode for the first capacitor and the second capacitor, wherein the second conductive electrode is a second shared bottom electrode for the third capacitor.

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