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1TnC memory bit-cell having stacked and folded planar capacitors with lateral offset

專利號
US11997853B1
公開日期
2024-05-28
申請人
Kepler Computing Inc.(US CA San Francisco)
發(fā)明人
Rajeev Kumar Dokania; Amrita Mathuriya; Debo Olaosebikan; Tanay Gosavi; Noriyuki Sato; Sasikanth Manipatruni
IPC分類
H10B53/30
技術(shù)領域
capacitors,capacitor,bit,in,electrode,node,layer,some,memory,wherein
地域: CA CA San Francisco

摘要

A configuration for efficiently placing a group of capacitors with one terminal connected to a common node is described. The capacitors are stacked and folded along the common node. In a stack and fold configuration, devices are stacked vertically (directly or with a horizontal offset) with one terminal of the devices being shared to a common node, and further the capacitors are placed along both sides of the common node. The common node is a point of fold. In one example, the devices are capacitors. N number of capacitors can be divided in L number of stack layers such that there are N/L capacitors in each stacked layer. The N/L capacitors are shorted together with an electrode (e.g., bottom electrode). The electrode can be metal, a conducting oxide, or a combination of a conducting oxide and a barrier material. The capacitors can be planar, non-planar or replaced by memory elements.

說明書

Example 7m: The apparatus of example 6m, wherein the metal layer is a shared bottom electrode for the plurality of memory elements, wherein the individual memory element includes a magnetic tunnelling junction, which comprises: a first magnet on the shared bottom electrode, the first magnet comprising one of CrO2, Heusler alloys, Fe, or CoFeB, the first magnet being a free magnet; a barrier material on the first magnet, the barrier material comprising one of: MgO, AlOx, or SrTiO3; a second magnet on the barrier material, the second magnet comprising one of CrO2, Heusler alloys, Fe, or CoFeB, the second magnet being a fixed magnet; and an anti-ferroelectric material on the second magnet, the anti-ferroelectric material comprising one of: Ru or Ir, or a super lattice of Co and Pt coupled with Ru and Jr, wherein the top electrode is coupled to the anti-ferroelectric material, wherein the shared bottom electrode and the top electrode include one of: Al, Ti, Cu, Ag, Pt, TiN, TaN, Al doped ZnO, Ga-doped ZnO, or Indium tin oxide (ITO).

Example 8m: The apparatus of example 6m, wherein the metal layer is a shared bottom electrode for the plurality of memory elements, wherein the individual memory element includes a resistive memory element, which comprises: an insulative material on the shared bottom electrode, the insulative material comprising HfOx, TiOx, TaOx, NiO, ZnOx, Zn2TiO4, KnOx, MgO, AlOx, ZrOx, CuxOy, SnOz, GeOx, LaOx, YOx, MoOx, or CoOx, where x and y are a number or a fraction, wherein the top electrode is on the insulative material, wherein the shared bottom electrode and the top electrode include one of: Al, Ti, Cu, Ag, Pt, TiN, TaN, Al doped ZnO, Ga-doped ZnO, or Indium tin oxide (ITO).

權(quán)利要求

1
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