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1TnC memory bit-cell having stacked and folded planar capacitors with lateral offset

專(zhuān)利號(hào)
US11997853B1
公開(kāi)日期
2024-05-28
申請(qǐng)人
Kepler Computing Inc.（US CA San Francisco）
發(fā)明人
Rajeev Kumar Dokania; Amrita Mathuriya; Debo Olaosebikan; Tanay Gosavi; Noriyuki Sato; Sasikanth Manipatruni
IPC分類(lèi)
H10B53/30
技術(shù)領(lǐng)域
capacitors,capacitor,bit,in,electrode,node,layer,some,memory,wherein
地域： CA CA San Francisco

摘要

A configuration for efficiently placing a group of capacitors with one terminal connected to a common node is described. The capacitors are stacked and folded along the common node. In a stack and fold configuration, devices are stacked vertically (directly or with a horizontal offset) with one terminal of the devices being shared to a common node, and further the capacitors are placed along both sides of the common node. The common node is a point of fold. In one example, the devices are capacitors. N number of capacitors can be divided in L number of stack layers such that there are N/L capacitors in each stacked layer. The N/L capacitors are shorted together with an electrode (e.g., bottom electrode). The electrode can be metal, a conducting oxide, or a combination of a conducting oxide and a barrier material. The capacitors can be planar, non-planar or replaced by memory elements.

說(shuō)明書(shū)

Example 11m: An apparatus comprising: a transistor having a gate terminal coupled to a word-line, a source terminal couple to a bit-line, and a drain terminal coupled to a storage node; a metal plane coupled to the storage node through a via; and a plurality of memory elements having bottom electrodes coupled to the metal plane, wherein an individual memory element of the plurality of memory elements has a top electrode which is coupled to an individual plate-line, wherein the plurality of memory elements are planar memory elements that are arranged in a staggered configuration on the metal plane such that a first memory element of the plurality of memory elements is offset along the metal plane diagonally from a second memory element of the plurality of memory elements, wherein the first memory element and the second memory element are on the metal plane.

Example 12m: The apparatus of example 11m, wherein the top electrode is coupled to the individual plate-line via a pedestal.

Example 13m: The apparatus of example 11m, wherein the individual memory element includes a magnetic tunneling junction, a resistive based memory element, or a phase-change based memory element.

Example 14m: The apparatus of example 11m, wherein the individual plate-line is parallel to the bit-line.

Example 15m: A system comprising: a processor circuitry to execute one or more instructions; a memory circuitry to store the one or more instructions; and a communication interface to allow the processor circuitry to communicate with another device, wherein the memory circuitry includes a plurality of bit-cells organized in a memory array, wherein an individual bit-cell of the plurality of bit-cells includes an apparatus according to any one of examples 1m to 10m, or examples 11m to 14m.

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