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1TnC memory bit-cell having stacked and folded planar capacitors with lateral offset

專利號
US11997853B1
公開日期
2024-05-28
申請人
Kepler Computing Inc.（US CA San Francisco）
發(fā)明人
Rajeev Kumar Dokania; Amrita Mathuriya; Debo Olaosebikan; Tanay Gosavi; Noriyuki Sato; Sasikanth Manipatruni
IPC分類
H10B53/30
技術領域
capacitors,capacitor,bit,in,electrode,node,layer,some,memory,wherein
地域： CA CA San Francisco

摘要

A configuration for efficiently placing a group of capacitors with one terminal connected to a common node is described. The capacitors are stacked and folded along the common node. In a stack and fold configuration, devices are stacked vertically (directly or with a horizontal offset) with one terminal of the devices being shared to a common node, and further the capacitors are placed along both sides of the common node. The common node is a point of fold. In one example, the devices are capacitors. N number of capacitors can be divided in L number of stack layers such that there are N/L capacitors in each stacked layer. The N/L capacitors are shorted together with an electrode (e.g., bottom electrode). The electrode can be metal, a conducting oxide, or a combination of a conducting oxide and a barrier material. The capacitors can be planar, non-planar or replaced by memory elements.

說明書

Example 4o: The apparatus of example 1o, wherein the second terminal of the individual memory element of the plurality of memory elements is coupled to the individual plate-line via an individual switch.

Example 5o: The apparatus of example 1o comprises a plurality of switches connected to the plurality of memory elements, wherein the plurality of switches is connected to a plurality of plate-lines, wherein the individual plate-line is among the plurality of plate-lines.

Example 6o: The apparatus of example 1o, wherein the metal layer comprises metal, a first conducting oxide, or a combination of a second conducting oxide and an insulative material.

Example 7o: The apparatus of example 1o, wherein the metal layer comprises metal.

Example 8o: The apparatus of example 1o, wherein the individual memory element includes a top electrode which is coupled to the individual plate-line.

Example 9o: The apparatus of example 8o, wherein the top electrode is coupled to the individual plate-line via a pedestal.

權利要求

1
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