FIG. 9A illustrates an apparatus comprising memory and corresponding logic, wherein the memory comprises FE memory bit-cells, where an individual memory bit-cell includes 1TnC bit-cells with PLs parallel to a BL, and with individual switches coupled to the capacitors on the plate-line side, where the corresponding logic is to apply word-line boosting, and wherein the capacitors are in a stacked and folded configuration, in accordance with some embodiments.
FIG. 9B illustrates an FE memory with word-line repeaters, wherein memory arrays include FE memory 1TnC bit-cells of FIG. 9A, in accordance with some embodiments.
FIG. 9C illustrates a timing diagram for write operation for 1T1C bit-cells with the PL parallel to the BL and where the word-lines (WLPs) for switch transistors for multiple plate-lines within a bit-cell are driven by a same signal, in accordance with some embodiments.
FIG. 9D illustrates a timing diagram for write operation for 1T1C bit-cells with the PL parallel to the BL and where the word-lines (WLPs) for switch transistors for multiple plate-lines within a bit-cell are driven by different signals, in accordance with some embodiments.
FIG. 9E illustrates a timing diagram for read operation for 1T1C bit-cells with the PL parallel to the BL and where the word-lines (WLPs) for switch transistors for multiple plate-lines within a bit-cell are driven by a same signal, in accordance with some embodiments.
