1TnC memory bit-cell having stacked and folded planar capacitors with lateral offset
摘要
說明書
While the various embodiments are illustrated with reference to n-type transistors or switches, the embodiments are also applicable to a p-type transistor or a combination of n-type or p-type transistors. A person skilled in the art would appreciate that when a transistor of a different conductivity type is used, than what is shown in
In some embodiments, the switches added to the plate-lines are fabricated in different layers of a die. For example, transistor MN1 is fabricated on the frontend of the die while transistors MNPLO_1, MNPLO_2, and MNPLO_n, are fabricated in the backend of the die. On one such embodiment, the capacitor Cfe is fabricated between the frontend and the backend of the die. In one example, capacitors Cfe are vertically stacked capacitors. In some embodiments, each switch and its corresponding coupled capacitor is formed in the backend of the die. In some embodiments, each switch and its corresponding coupled capacitor is stacked vertically. For example, transistor MNPLO_1 and capacitor Cfe1 are stacked vertically in a first vertical stack, and transistor MNPLO_2 and capacitor Cfe2 are stacked vertically in a second vertical stack. These backed transistors or switches can be fabricated using any suitable technology such as IGZO (Indium gallium zinc oxide).
