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1TnC memory bit-cell having stacked and folded planar capacitors with lateral offset

專利號
US11997853B1
公開日期
2024-05-28
申請人
Kepler Computing Inc.（US CA San Francisco）
發(fā)明人
Rajeev Kumar Dokania; Amrita Mathuriya; Debo Olaosebikan; Tanay Gosavi; Noriyuki Sato; Sasikanth Manipatruni
IPC分類
H10B53/30
技術(shù)領(lǐng)域
capacitors,capacitor,bit,in,electrode,node,layer,some,memory,wherein
地域： CA CA San Francisco

摘要

A configuration for efficiently placing a group of capacitors with one terminal connected to a common node is described. The capacitors are stacked and folded along the common node. In a stack and fold configuration, devices are stacked vertically (directly or with a horizontal offset) with one terminal of the devices being shared to a common node, and further the capacitors are placed along both sides of the common node. The common node is a point of fold. In one example, the devices are capacitors. N number of capacitors can be divided in L number of stack layers such that there are N/L capacitors in each stacked layer. The N/L capacitors are shorted together with an electrode (e.g., bottom electrode). The electrode can be metal, a conducting oxide, or a combination of a conducting oxide and a barrier material. The capacitors can be planar, non-planar or replaced by memory elements.

說明書

FIG. 13B illustrates a 1TnC bit-cell with stacked and folded planar capacitors that use extended bottom electrodes and aligned central pedestals, in accordance with some embodiments.

FIG. 13C illustrates a 1TnC bit-cell with stacked and folded planar capacitors having offset and that use extended bottom electrodes and with aligned central pedestals, in accordance with some embodiments.

FIG. 13D illustrates a 1TnC bit-cell used for FIGS. 13A-C, in accordance with some embodiments.

FIG. 14A illustrates a 1TnC bit-cell with stacked and folded planar capacitors that use extended shared metal and misaligned central pedestals, in accordance with some embodiments.

FIG. 14B illustrates a 1TnC bit-cell with stacked and folded planar capacitors that use extended shared metal and aligned central pedestals, in accordance with some embodiments.

FIG. 14C illustrates a 1TnC bit-cell with stacked and folded planar capacitors having offset and that use extended shared metal and with aligned central pedestals, in accordance with some embodiments.

FIG. 14D illustrates a top view cross-section of a capacitor placement configuration where planar capacitors are staggered on a shared bottom electrode or shared metal, in accordance with some embodiments.

FIG. 15A illustrates a 1TnC bit-cell with stacked and folded non-planar capacitors, in accordance with some embodiments.

權(quán)利要求

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