FIG. 9E illustrates timing diagram 950 for read operation for 1T1C bit-cells with the PL parallel to the BL and where the word-lines (WLPs) for switch transistors for multiple plate-lines within a bit-cell are driven by a same signal, in accordance with some embodiments. In some embodiments, read operation begins by asserting the selected WL. In some embodiments, the selected WL is boosted for read operation. WL is boosted above Vdd to Vdd+Vboost level. In some embodiments, a writeback scheme is implemented after the read operation to restore the data value stored in the selected bit-cell due to the destructive nature of the read operation. In one such embodiment, the data which is read is also written back in the writeback time window after the read time window. In some embodiments, PL (e.g., PL0_1) is asserted for the bit-cell which is being read. Other unselected PLs (e.g., PL0_2, PL_3, . . . PL0_n) of the bit-cell are kept at 0V during read operation, and then to Vdd/2 during writeback if the first scheme is followed. Here, here, ‘x’ in PLx_n indicates the same orientation as BL. For example, plate-lines PL0_1, PL0_2, and PL0_3 are parallel to BL0. Likewise, plate-lines PL1_1, PL1_2, and PL1_3 are parallel to BL1, and so on.
