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1TnC memory bit-cell having stacked and folded planar capacitors with lateral offset

專利號(hào)
US11997853B1
公開(kāi)日期
2024-05-28
申請(qǐng)人
Kepler Computing Inc.（US CA San Francisco）
發(fā)明人
Rajeev Kumar Dokania; Amrita Mathuriya; Debo Olaosebikan; Tanay Gosavi; Noriyuki Sato; Sasikanth Manipatruni
IPC分類
H10B53/30
技術(shù)領(lǐng)域
capacitors,capacitor,bit,in,electrode,node,layer,some,memory,wherein
地域： CA CA San Francisco

摘要

A configuration for efficiently placing a group of capacitors with one terminal connected to a common node is described. The capacitors are stacked and folded along the common node. In a stack and fold configuration, devices are stacked vertically (directly or with a horizontal offset) with one terminal of the devices being shared to a common node, and further the capacitors are placed along both sides of the common node. The common node is a point of fold. In one example, the devices are capacitors. N number of capacitors can be divided in L number of stack layers such that there are N/L capacitors in each stacked layer. The N/L capacitors are shorted together with an electrode (e.g., bottom electrode). The electrode can be metal, a conducting oxide, or a combination of a conducting oxide and a barrier material. The capacitors can be planar, non-planar or replaced by memory elements.

說(shuō)明書(shū)

The PL for the selected capacitor of the bit-cell is asserted for a time period long enough for the sense amplifier to sense the value stored on the storage node coupled to the capacitor. In various embodiments, sense amplifier enable signal (SAE) is asserted within the pulse width of the PL. In some embodiments, to read data from the storage node, BLx (e.g., BL0) is set or forced to zero volts during read operation, and then set to ? Vdd just before WL is boosted for write back operation when the first scheme is followed. Writeback operation for the first scheme is like the write operation discussed with reference to FIG. 9C.

Referring to FIG. 9E, in some embodiments, storage node sn1 of the selected bit-cell SNx is precharged via BL and then floated. Here, “floating” means that there is no active driver for the node. In this case, the precharged voltage value acts as the initial bias voltage, which can then go down or up depending upon leakage characteristics at that node, or due to ferroelectric capacitors on the SNx node interacting with the read mechanism associated with PL pulsing. In various embodiments, selected BLx (e.g., BL0) follows similar characteristics as SNx during the read phase.

At that point the PL (e.g., PL0_1) for the desired FE capacitor is toggled, which results into voltage buildup on the SNx node. The voltage build-up on the SNx node may be different voltage levels depending upon whether the FE capacitor state was logic 0 or logic 1. The time-sampling of this voltage relative to a reference expected value, results in detection of the state in which the FE capacitor was programmed. After reading the value, a write-back operation can be done to get the value restored to the FE capacitor, as reads are destructive read in this configuration, in accordance with some embodiments.

權(quán)利要求

1
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