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1TnC memory bit-cell having stacked and folded planar capacitors with lateral offset

專利號
US11997853B1
公開日期
2024-05-28
申請人
Kepler Computing Inc.（US CA San Francisco）
發(fā)明人
Rajeev Kumar Dokania; Amrita Mathuriya; Debo Olaosebikan; Tanay Gosavi; Noriyuki Sato; Sasikanth Manipatruni
IPC分類
H10B53/30
技術(shù)領(lǐng)域
capacitors,capacitor,bit,in,electrode,node,layer,some,memory,wherein
地域： CA CA San Francisco

摘要

A configuration for efficiently placing a group of capacitors with one terminal connected to a common node is described. The capacitors are stacked and folded along the common node. In a stack and fold configuration, devices are stacked vertically (directly or with a horizontal offset) with one terminal of the devices being shared to a common node, and further the capacitors are placed along both sides of the common node. The common node is a point of fold. In one example, the devices are capacitors. N number of capacitors can be divided in L number of stack layers such that there are N/L capacitors in each stacked layer. The N/L capacitors are shorted together with an electrode (e.g., bottom electrode). The electrode can be metal, a conducting oxide, or a combination of a conducting oxide and a barrier material. The capacitors can be planar, non-planar or replaced by memory elements.

說明書

FIG. 10C illustrates timing diagram 1030 for write operation for multi-element FE gain bit-cells with the PL parallel to the BL and where the word-lines (WLPs) for switch transistors for multiple plate-lines within a bit-cell are driven by a same signal, in accordance with some embodiments. In this scheme (first scheme) all WLPs for switch transistors are driven by a same signal per bit-cell, in accordance with some embodiments. For example, WLP0_1, WLP0_2, . . . WLP0_n for bit-cell 10010,0 share a same signal driver. In some embodiments, the signals on WLPs for switch transistors for a bit-cell during the write operation are same as the WL0 signal for that bit-cell.

To write to a capacitor of a multi-element FE gain bit-cell (e.g., 10010,0), WL to that bit-cell is boosted. For example, WL0 is boosted to Vdd+Vboost. In some embodiments, the BL (e.g., BLx) for multi-element FE gain bit-cell is set to ? Vdd during the time the WL (e.g., WL0) is boosted. In some embodiments, the BLx (e.g., BL0) is set to ? Vdd prior to the WL boosting. In some embodiments, BLx remains charged to ? Vdd even after WL0 boosting ends (e.g., for one or more cycles). To program a particular capacitor of the multi-element FE gain bit-cell, the plate-line for that capacitor is first set to ? Vdd and then set to Vdd or ground during the pulse width of the boosted WL to store a 0 or a 1 to that capacitor. In this example, PL0_1 is charged from 0V to Vdd/2 when BL0 is charged to Vdd/2. Then during the pulse width of the boosted WL, PL0_1 is set to Vdd to write a 0 to capacitor Cfe1. In some embodiments, during the pulse width of the boosted WL, PL0_1 is set to 0V to write a 1 to the capacitor Cfe1.

權(quán)利要求

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