The timing controller 13 receives digital video data DATA of an input image and timing signals synchronized with the digital video data DATA from a host system. The timing signals may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a clock signal DCLK, a data enable signal DE and the like. The host system may be any one of various electronic devices such as a television system, a set-top box, a navigation system, a digital video disc (DVD) player, a Blu-ray player, a personal computer (PC), a home theater system, a phone system, and the like.

The timing controller 13 may generate a data timing control signal DDC for controlling an operational timing of the data driver 12, MUX selection signals for controlling an operational timing of the multiplexer 14, and a gate timing control signal GDC for controlling an operational timing of the gate driver 11 based on the timing signals Vsync, Hsync, DCLK and DE that are received from the host system.

The data timing control signal DDC may include a source start pulse SSP, a source sampling clock SSC, a polarity control signal POL, and a source output enable signal SOE, and the like. The source start pulse SSP controls a sampling start timing of the data driver 12. The source sampling clock SSC is a clock for shifting a data sampling timing. The polarity control signal POL controls polarity of a data signal output from the data driver 12. If a signal transmission interface between the timing controller 13 and the data driver 12 is a mini-LVDS (low voltage differential signaling) interface, the source start pulse SSP and the source sampling clock SSC may be omitted.