A first interlayer insulating layer 160 is formed on the first gate electrode 154a, the second gate electrode 154b, and the second capacitor electrode 158.
A first source contact hole 166a exposing the first source region 1356a of the first semiconductor 135a, a first drain contact hole 167a exposing the first drain region 1357a of the first semiconductor 135a, a second source contact hole 166b exposing the second source region 1356b of the second semiconductor 135b, and a second drain contact hole 167b exposing the second drain region 1357b of the second semiconductor 135b are formed in the first interlayer insulating layer 160 and the gate insulating layer 140. A first contact hole 81 exposing the second gate electrode 154b is formed in the first interlayer insulating layer 160.
A data line 171 including the first source electrode 176a, a driving voltage line 172 including a second source electrode 176b, a first drain electrode 177a and a second drain electrode 177b, and a third capacitor electrode 178 are formed on the first interlayer insulating layer 160.
The first source electrode 176a is connected with the first source region 1356a through the first source contact hole 166a, and the second source electrode 176b is connected with the second source region 1356b through the second source contact hole 166b.