A buffer layer 120 is formed on a substrate 100, and a first semiconductor 135a and a second semiconductor 135b made of polysilicon, as well as a first capacitor electrode 138, are formed on the buffer layer 120.
The first semiconductor 135a includes a first channel region 1355a, and a first source region 1356a and a first drain region 1357a which are formed at both sides of the first channel region 1355a.
The second semiconductor 135b includes a second channel region 1355b, and a second source region 1356b and a second drain region 1357b which are formed at both sides of the second channel region 1355b.
The first capacitor electrode 138 is extended from the second source region 1356b of the second semiconductor 135b.
A gate insulating layer 140 is formed on the first semiconductor 135a and the second semiconductor 135b, as well as the first capacitor electrode 138.
A gate line 121, a first gate electrode 154a, a second gate electrode 154b, and a second capacitor electrode 158 are formed on the gate insulating layer 140.
The gate line 121 is elongated in a horizontal direction to transfer a gate signal, and the first gate electrode 154a protrudes toward the first semiconductor 135a from the gate line 121.