As compared to the TFT structure of FIGS. 6A and 6B, the TFT in FIGS. 6C-E includes less of the second insulator. This will reduce parasitic capacitance and can improve device performance.
FIGS. 20A-20C are top and cross-sectional views (through I-J and K-L) of an embodiment of FIG. 2 that includes a pixel visual element 2020 coupled to a first AMNR 2022, a second AMNR 2024, and an AMTFT 2026. The AMTFT 2026 includes a first amorphous metal or amorphous metal alloy electrode 2028 on a substrate 2030. First and second dielectric layers 2032, 2034 are formed on the electrode 2028. The AMTFT 2026 includes a semiconductor layer, i.e., an electrode 2036 that is between the first dielectric 2032 and the second dielectric layer 2034. The electrode 2036 overlaps a portion of the electrode 2028.
Another electrode 2038 overlaps the electrodes 2036 and 2028. The electrode 2038 extends from an edge that aligns with an edge 2035 of the electrode 2028 to a location between and coupled to the first and second AMNRs 2022, 2024. A third dielectric layer 2040 is on top of the electrode 2038.
