Display apparatus
地域：
Seoul
摘要
A display apparatus includes a first TFT in a display area including a first semiconductor pattern including a polysilicon, a first gate electrode overlapping with the first semiconductor pattern under conditions that a first gate insulating layer is interposed, and first source and drain electrodes connected to the first semiconductor pattern, a second TFT in the display area including a second semiconductor pattern including a first oxide semiconductor, a second gate electrode overlapping with the second semiconductor pattern under conditions that second and third gate insulating layers are interposed, second source and drain electrodes connected to the second semiconductor pattern, and a third TFT in a non-display area including a third semiconductor pattern including a second oxide semiconductor, a third gate electrode overlapping with the third semiconductor pattern under conditions that the third gate insulating layer is interposed, and third source and drain electrodes connected to the third semiconductor pattern.
說明書
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This application is a continuation of U.S. patent application Ser. No. 17/126,547 filed on Dec. 18, 2020, which claims the benefit of Republic of Korea Patent Application No. 10-2019-0180051 filed on Dec. 31, 2019, each of which is hereby incorporated by reference in its entirety.
The present disclosure relates to a display apparatus including thin film transistors.
Generally, an electric appliance such as a monitor, a television (TV), a notebook computer, or a digital camera includes a display apparatus configured to realize an image. For example, display apparatuses may include a liquid crystal display (LCD) apparatus including liquid crystals and an electroluminescent display (ELD) apparatus including a light emitting layer.
Among such display apparatuses, the ELD apparatus uses a self-luminous device configured to emit light by itself.
A display apparatus may include a plurality of pixels. Each pixel may emit a particular color. A driving device may be disposed in each pixel in order to generate drive current according to a gate signal and a data signal. For example, the driving device may include at least one thin film transistor.
權(quán)利要求
What is claimed is:1. A display apparatus comprising:a substrate comprising a display area and a non-display area that is adjacent to the display area; a second thin film transistor in the display area of the substrate, the second thin film transistor comprising a second semiconductor pattern comprising a second oxide semiconductor, a second gate electrode overlapping the second semiconductor pattern such that a second gate insulating layer is interposed between the second gate electrode and the second semiconductor pattern, a second source electrode connected to the second semiconductor pattern, and a second drain electrode connected to the second semiconductor pattern; a first conductive pattern between the display area of the substrate and the second semiconductor pattern of the second thin film transistor; and a second buffer layer including a silicon nitride layer interposed between the second semiconductor pattern and the first conductive pattern, wherein the first conductive pattern is connected to any of the second source electrode and the second drain electrode. 2. The display apparatus according to claim 1 , further comprising:a first thin film transistor in the display area of the substrate, the first thin film transistor comprising a first semiconductor pattern comprising a first polysilicon on a first buffer layer, a first gate electrode overlapping the first semiconductor pattern such that a first gate insulating layer is interposed between the first gate electrode and the first semiconductor pattern, a first source electrode connected to the first semiconductor pattern, and a first drain electrode connected to the first semiconductor pattern. 3. The display apparatus according to claim 2 , wherein the second thin film transistor is a driving thin film transistor and the first thin film transistor is a switching thin film transistor. 4. The display apparatus according to claim 2 , further comprising:a fourth thin film transistor disposed in the non-display area of the substrate, the fourth thin film transistor comprising a fourth semiconductor pattern comprising a second polysilicon on the first buffer layer, a fourth gate electrode overlapping the fourth semiconductor pattern such that the first gate insulating layer is interposed between the fourth gate electrode and the fourth semiconductor pattern, a fourth source electrode connected to the fourth semiconductor pattern, and a fourth drain electrode connected to the fourth semiconductor pattern. 5. The display apparatus according to claim 4 , wherein the first conductive pattern is connected to any one of the second source electrode and the second drain electrode by a first connecting electrode, and the second conductive pattern is connected to any one of the fourth source electrode and the fourth drain electrode by a second connecting electrode. 6. The display apparatus according to claim 1 , further comprising:a third thin film transistor disposed in the non-display area of the substrate, the third thin film transistor comprising a third semiconductor pattern comprising a second oxide semiconductor, a third gate electrode overlapping the third semiconductor pattern, a third source electrode connected to the third semiconductor pattern, and a third drain electrode connected to the third semiconductor pattern; and a second conductive pattern between the non-display area of the substrate and the third semiconductor pattern of the third thin film transistor, wherein the second buffer layer extends to the non-display area and is interposed between the third semiconductor pattern and the second conductive pattern. 7. The display apparatus according to claim 6 , wherein the second conductive pattern is connected to any of the third source electrode and the third drain electrode. 8. The display apparatus according to claim 6 , wherein a first thickness of an insulating layer between the second semiconductor pattern and the first conductive pattern is less than a second thickness of an insulating layer between the third semiconductor pattern and the second conductive pattern. 9. The display apparatus according to claim 6 , wherein the first thin film transistor is a driving thin film transistor and the third thin film transistor is a thin film transistor that performs a switching function of gate signals. 10. The display apparatus according to claim 6 , a third thickness of an insulating layer between the second semiconductor pattern and the second gate electrode is greater than a fourth thickness of an insulating layer between the third semiconductor pattern and the third gate electrode. 11. The display apparatus according to claim 6 , wherein the second semiconductor pattern and the third semiconductor pattern are disposed on a different layer each other. 12. A display apparatus comprising:a substrate comprising a display area and a non-display area that is adjacent to the display area; a first thin film transistor in the display area, the first thin film transistor comprising a first semiconductor pattern comprising a first oxide semiconductor, a first gate electrode overlapping the first semiconductor pattern, a first source electrode connected to the first semiconductor pattern, and a first drain electrode connected to the first semiconductor pattern; a second thin film transistor in the display area, the second thin film transistor comprising a second semiconductor pattern comprising a second oxide semiconductor, a second gate electrode overlapping the second semiconductor pattern, a second source electrode connected to the second semiconductor pattern, and a second drain electrode connected to the second semiconductor pattern; a third thin film transistor in the non-display area, the third thin film transistor comprising a third semiconductor pattern comprising a third oxide semiconductor, a third gate electrode overlapping the third semiconductor pattern, a third source electrode connected to the third semiconductor pattern, and a third drain electrode connected to the third semiconductor pattern; a first conductive pattern under the first semiconductor pattern and overlapping with the first semiconductor pattern; a second conductive pattern under the second semiconductor pattern and overlapping with the second semiconductor pattern; and a third conductive pattern under the third semiconductor pattern and overlapping with the third semiconductor pattern; wherein a first thickness of an insulating layer between the first semiconductor pattern and the first conductive pattern is less than a second thickness of an insulating layer between the second semiconductor pattern and the second conductive pattern. 13. The display apparatus according to claim 12 , wherein the first semiconductor pattern and the second semiconductor pattern are on a different layer from each other. 14. The display apparatus according to claim 12 , wherein the first conductive pattern, the second conductive pattern, and the third conductive pattern are a single layer or multilayers including titanium. 15. The display apparatus according to claim 12 , further comprising:a buffer layer covering the first conductive pattern, the second conductive pattern, and the third conductive pattern. 16. The display apparatus according to claim 15 , wherein the buffer layer is multilayer including a silicon nitride layer. 17. The display apparatus according to claim 15 , wherein the first conductive pattern, the second conductive pattern, and the third conductive pattern are on a same layer. 18. The display apparatus according to claim 17 , wherein the first thin film transistor is driving thin film transistor, the second thin film transistor is switching thin film transistor, and the third thin film transistor is configured to perform a switching function of gate signals. 19. A display apparatus comprising:a substrate comprising a display area and a non-display area that is adjacent to the display area; a first thin film transistor in the display area of the substrate, the first thin film transistor comprising a first semiconductor pattern comprising a first oxide semiconductor, a first gate electrode overlapping the first semiconductor pattern such that a second gate insulating layer is interposed between the first gate electrode and the first semiconductor pattern, a first source electrode connected to the first semiconductor pattern, and a first drain electrode connected to the first semiconductor pattern; a second thin film transistor in the display area of the substrate, the second thin film transistor comprising a second semiconductor pattern comprising a second oxide semiconductor, a second gate electrode overlapping the second semiconductor pattern, a second source electrode connected to the second semiconductor pattern, and a second drain electrode connected to the second semiconductor pattern; a third thin film transistor in the non-display area of the substrate, the third thin film transistor comprising a third semiconductor pattern comprising a first polysilicon on a first buffer layer, a third gate electrode overlapping the third semiconductor pattern such that a first gate insulating layer is interposed between the third gate electrode and the third semiconductor pattern, a third source electrode connected to the third semiconductor pattern, and a third drain electrode connected to the third semiconductor pattern; a first conductive pattern between the display area of the substrate and the first semiconductor pattern of the first thin film transistor; a second conductive pattern between the display area of the substrate and the second semiconductor pattern of the second thin film transistor; and a second buffer layer including a silicon nitride layer interposed between the first semiconductor pattern and the first conductive pattern, wherein a first thickness of an insulating layer between the first semiconductor pattern and the first conductive pattern is less than a second thickness of an insulating layer between the second semiconductor pattern and the second conductive pattern.
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