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Intelligent in-rack pump or compressor unit for datacenter cooling systems

專利號(hào)
US12082382B2
公開日期
2024-09-03
申請(qǐng)人
Nvidia Corporation（US CA Santa Clara）
發(fā)明人
Ali Heydari
IPC分類
H05K7/20; G05B13/02
技術(shù)領(lǐng)域
least,in,at,embodiment,or,may,cooling,network,be,rack
地域： CA CA Santa Clara

摘要

Systems and methods for cooling a datacenter are disclosed. In at least one embodiment, a control unit within a rack has a pump or compressor unit to cause two-phase fluid to circulate through a cold plate associated with a computing device and to circulate through a heat exchanger associated with a rear door of a rack, so as to dissipate heat from a computing device through a heat exchanger by a control unit within a rack.

說(shuō)明書

In at least one embodiment, multiple instances of GPGPU 3530 can be configured to operate as a compute cluster. In at least one embodiment, compute clusters 3536A-3536H may implement any technically feasible communication techniques for synchronization and data exchange. In at least one embodiment, multiple instances of GPGPU 3530 communicate over host interface 3532. In at least one embodiment, GPGPU 3530 includes an I/O hub 3539 that couples GPGPU 3530 with a GPU link 3540 that enables a direct connection to other instances of GPGPU 3530. In at least one embodiment, GPU link 3540 is coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances of GPGPU 3530. In at least one embodiment GPU link 3540 couples with a high speed interconnect to transmit and receive data to other GPGPUs 3530 or parallel processors. In at least one embodiment, multiple instances of GPGPU 3530 are located in separate data processing systems and communicate via a network device that is accessible via host interface 3532. In at least one embodiment GPU link 3540 can be configured to enable a connection to a host processor in addition to or as an alternative to host interface 3532. In at least one embodiment, GPGPU 3530 can be configured to execute a CUDA program.

FIG. 36A illustrates a parallel processor 3600, in accordance with at least one embodiment. In at least one embodiment, various components of parallel processor 3600 may be implemented using one or more integrated circuit devices, such as programmable processors, application specific integrated circuits (“ASICs”), or FPGAs.

權(quán)利要求

1
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