In at least one embodiment, each processing cluster 3694 may include an MMU 3645 that is configured to map virtual addresses into physical addresses. In at least one embodiment, one or more instances of MMU 3645 may reside within memory interface 3618 of FIG. 36. In at least one embodiment, MMU 3645 includes a set of page table entries (“PTEs”) used to map a virtual address to a physical address of a tile and optionally a cache line index. In at least one embodiment, MMU 3645 may include address translation lookaside buffers (“TLBs”) or caches that may reside within graphics multiprocessor 3634 or L1 cache 3648 or processing cluster 3694. In at least one embodiment, a physical address is processed to distribute surface data access locality to allow efficient request interleaving among partition units. In at least one embodiment, a cache line index may be used to determine whether a request for a cache line is a hit or miss.
