In the QLC mode, as illustrated in FIG. 4A, the control range of threshold voltages (the range from Vmin to Vmax) is divided into 16 states (small areas) ST0 to ST15. Different 4-bit values are associated with each of the states ST0 to ST15.

In the example of FIG. 4A, the 16 states ST0 to ST15 correspond to 4-bit values of “1111”, “1110”, “1101”, “1100”, “1011”, “1010”, “1001”, “1000”, “0111”, “0110”, “0101”, “0100”, “0011”, “0010”, “0001”, and “0000” from the side with the lowest voltage.

The four bits corresponding to each of the states ST, from the upper-order bit side to the lower-order bit side, represent the bit value included in the page PG0, the bit value included in the page PG1, the bit value included in the page PG2, and the bit value included in the page PG3, respectively.

During the program process, the threshold voltage of the memory cell MT to be programmed is controlled to belong to one of the 16 states ST0 to ST15 corresponding to the data to be programmed therein. The threshold voltage of the plurality of memory cells MT in the page or block after the program process may be represented as 16 distributions, each having the lobe shape illustrated in FIG. 4A, and separated by read voltages (Vread0 to Vread14), where the horizontal axis represents a range of threshold voltages, from low to high, and the vertical axis represents the number of memory cells that have the threshold voltages represented by the horizontal axis. A memory cell MT programmed in the QLC mode is also referred to as a quad-level cell (QLC).