During the period from timings t6 to t7, the selected word line WL transitions from the program voltage V_PGM to the reference voltage V_SS1, and the non-selected word line WL corresponding to the PLC transitions from the program pass voltage V_PASS1 to the reference voltage V_SS1, the non-selected word line WL corresponding to the QLC transitions from the program pass voltage V_PASS2 to the reference voltage V_SS1, and the selected drain side select gate line SGD transitions from the selected voltage V_SGD to the reference voltage V_SS2. As a result, the program operation to the memory cell MT is completed.

During the period from the timings t1 to t7, the source side select gate line SGS is maintained at the reference voltage V_SS3.

Next, the program disturb and the VPASS disturb will be described with reference to FIGS. 2 and 6 to 8. For example, among the bit lines BL0 to BL2 illustrated in FIGS. 2, 6, and 7, the selected voltage V_SS4 (e.g., 0 V) is applied to the bit line BL0, and the write-inhibited voltage V_INHIBIT (e.g., 2.5 V) is applied to the other bit lines BL1 and BL2. Among the drain side select gate lines SGD0 to SGD3 illustrated in FIG. 2, the selected voltage V_SGD (e.g., 2.5 V) is applied to the drain side select gate line SGD0, and the non-selected voltage V_SS2 (e.g., 0 V) is applied to the other drain side select gate lines SGD1, SGD2, and SGD3.