As illustrated in FIG. 6, in Reference Example in which no shield electrode A1 is provided, the potential of the conductor LE (and the gate electrode GE) is boosted at the timing of switching between the vertical scanning period VT and the update pause period PT (the timing at which the potential of the data signal line DLi shifts from the white gray scale level to the applied voltage level). Thus, the luminance difference between the refresh frame period RT and the non-refresh frame period NT in the subpixel SP becomes large, so that the low-frequency flicker may be visually recognized.

In the first embodiment, the shield electrode A1 is included in the first metal layer K1, so that it is less likely to be short-circuited with the data signal line DLi included in the fourth metal layer K4 and the conductor LE included in the second metal layer K2.

In addition, the scanning signal line GXn is selected (the transistor T3 is turned on) and a bias (applied voltage level) is applied to the source electrode of the transistor T4 also in the update pause period PT, and thus the luminance difference between the refresh frame period RT and the non-refresh frame period NT is further suppressed. The constant potential signal (applied voltage level) in the update pause period PT only need be set to a predetermined level from the white gray scale level to the black gray scale level.