Semiconductor devices and data storage systems including the same
地域：
Suwon-si
摘要
A semiconductor device includes a substrate; a stack structure on the substrate and including an alternating stack of interlayer insulating layers and gate electrodes; first and second separation regions each extending through the stack structure and extending in a first direction; a first upper separation region between the first and second separation regions and extending through a portion of the stack structure; a plurality of channel structures between the first and second separation regions and extending through the stack structure; and a plurality of first vertical structures each extending through a particular one of the first and second separation regions. Each of the first and second separation regions has a first width in a second direction that is perpendicular to the first direction. Each first vertical structure has a second width in the second direction, the second width being greater than the first width.
說明書
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This application claims benefit of priority to Korean Patent Application No. 10-2020-0123056 filed on Sep. 23, 2020 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.
The present inventive concepts relate to semiconductor devices and data storage systems including the same.
In a data storage system requiring data storage, a semiconductor device capable of storing high-capacity data is required. Accordingly, methods of increasing data storage capacity of a semiconductor device are being studied. For example, as one method for increasing data storage capacity of a semiconductor device, a semiconductor device including three-dimensionally arranged memory cells, instead of two-dimensionally arranged memory cells, has been proposed.
Some example embodiments of the present inventive concepts provide a semiconductor device having improved reliability.
Some example embodiments of the present inventive concepts provide a data storage system including a semiconductor device having improved reliability.
權(quán)利要求
What is claimed is:1. A semiconductor device comprising:a substrate; a stack structure on the substrate, the stack structure including an alternating stack of interlayer insulating layers and gate electrodes; a first separation region and a second separation region, each of the first separation region and the second separation region extending through the stack structure, such that the first separation region and the second separation region are connected to the substrate and extend in a first direction; a first upper separation region between the first separation region and the second separation region and extending through a portion of the stack structure; a plurality of channel structures between the first separation region and the second separation region and extending through the stack structure; and a plurality of first vertical structures respectively extending through the first separation region and the second separation region, wherein each of the first and second separation regions has a first width in a second direction, the second direction being perpendicular to the first direction, and wherein each of the plurality of first vertical structures has a second width in the second direction, the second width being greater than the first width. 2. The semiconductor device of claim 1 , further comprising:a plurality of second vertical structures respectively extending through the first and second separation regions, wherein each of the plurality of second vertical structures has a third width, greater than the second width, in the second direction, and the plurality of second vertical structures and the plurality of first vertical structures are alternately arranged in the first direction. 3. The semiconductor device of claim 1 , further comprising a third vertical structure extending through the stack structure and contacting the first upper separation region. 4. The semiconductor device of claim 3 , wherein the third vertical structure is isolated from direct contact with any one lateral surface among opposite lateral surfaces of the first upper separation region. 5. The semiconductor device of claim 3 , wherein a width of the third vertical structure is substantially identical to the second width of each of the plurality of first vertical structures. 6. The semiconductor device of claim 1 , whereinthe plurality of channel structures includes a first channel structure and a second channel structure, one first vertical structure among the plurality of first vertical structures, the first channel structure, and the second channel structure are sequentially arranged in a third direction, the third direction being a diagonal direction between the first direction and the second direction, the first channel structure is adjacent to the one first vertical structure in the third direction, and the first channel structure is between the one first vertical structure and the second channel structure, a center of the first channel structure is spaced apart from a center of the one first vertical structure by a first distance, and a center of the second channel structure is spaced apart from the center of the first channel structure by a second distance, the second distance being less than the first distance. 7. The semiconductor device of claim 6 , whereinthe plurality of channel structures further includes a third channel structure and a fourth channel structure, the third channel structure is adjacent to the one first vertical structure in a fourth direction, the fourth direction being perpendicular to the third direction, the third channel structure is adjacent to the first channel structure in the first direction, and the third channel structure is between the fourth channel structure and the first channel structure, a center of the third channel structure is spaced apart from the center of the first channel structure by a third distance in the first direction, and a center of the fourth channel structure is spaced apart from the center of the third channel structure by a fourth distance in the first direction, the fourth distance being less than the third distance. 8. The semiconductor device of claim 1 , whereinthe plurality of channel structures includes a first channel structure and a second channel structure, one first vertical structure among the plurality of first vertical structures, the first channel structure, and the second channel structure are sequentially arranged in a third direction, the third direction being a diagonal direction between the first direction and the second direction, the first channel structure is adjacent to the one first vertical structure in the third direction, and the first channel structure is between the one first vertical structure and the second channel structure, a center of the first channel structure is spaced apart from a center of the one first vertical structure by a first distance, and a center of the second channel structure is spaced apart from the center of the first channel structure by a second distance, the second distance being substantially equal to the first distance. 9. The semiconductor device of claim 8 , whereinthe plurality of channel structures further includes a third channel structure and a fourth channel structure, the third channel structure is adjacent to the one first vertical structure in a fourth direction, the fourth direction being perpendicular to the third direction, the third channel structure being adjacent to the first channel structure in the first direction, and the third channel structure being between the fourth channel structure and the first channel structure, a center of the third channel structure is spaced apart from the center of the first channel structure by a third distance in the first direction, and a center of the fourth channel structure is spaced apart from the center of the third channel structure by a fourth distance in the first direction, the fourth distance being substantially equal to the third distance. 10. The semiconductor device of claim 1 , whereinthe plurality of channel structures includes at least three channel structures sequentially arranged in the second direction, a portion of the first upper separation region is between a pair of channel structures adjacent to each other in the second direction, among the at least three channel structures, and a distance between the pair of channel structures is greater than a distance between any one channel structure adjacent to the pair of channel structures in the second direction and the pair of channel structures. 11. The semiconductor device of claim 1 , further comprising a second upper separation region between the first upper separation region and the second separation region. 12. The semiconductor device of claim 1 , wherein a width of each of the plurality of first vertical structures in the first direction is different from the second width of each of the plurality of first vertical structures in the second direction. 13. The semiconductor device of claim 1 , further comprising:a peripheral circuit structure including a base substrate and a peripheral circuit on the base substrate, wherein the substrate is on the peripheral circuit structure. 14. The semiconductor device of claim 1 , further comprising:a peripheral circuit structure; bit lines; and first bonding pads, wherein the bit lines are electrically connected to the plurality of channel structures between the peripheral circuit structure and the stack structure, at least a portion of the first bonding pads are between the bit lines and the peripheral circuit structure, and the peripheral circuit structure includes second bonding pads contacting and bonded to the first bonding pads, a peripheral circuit on the second bonding pads, and a base substrate on the peripheral circuit. 15. A semiconductor device, comprising:a substrate; a stack structure on the substrate, the stack structure including an alternating stack of interlayer insulating layers and gate electrodes, alternately stacked in a direction perpendicular to an upper surface of the substrate; separation regions having a first width and extending through the stack structure, such that the separation regions are connected to the substrate and further extend in a first direction; a plurality of channel structures extending through the stack structure; and a plurality of vertical structures extending through the stack structure, wherein at least one vertical structure among the plurality of vertical structures extends through at least one separation region of the separation regions, and wherein the at least one vertical structure among the plurality of vertical structures has a second width greater than the first width. 16. The semiconductor device of claim 15 , further comprising:a plurality of upper separation regions between the separation regions and extending through a portion of the stack structure, wherein at least a portion of the plurality of vertical structures extend through one or more upper separation regions of the plurality of upper separation regions, and the plurality of vertical structures and the plurality of channel structures are alternately arranged in a second direction, the second direction being perpendicular to the first direction. 17. The semiconductor device of claim 15 , whereineach of the separation regions has the first width in a second direction, the second direction being perpendicular to the first direction, and each of the plurality of vertical structures have the second width in the second direction. 18. The semiconductor device of claim 15 , whereinthe plurality of channel structures includes a first channel structure and a second channel structure, the first channel structure is adjacent to one vertical structure among the plurality of vertical structures in the first direction and in a third direction, the third direction being a diagonal direction between the first direction and a second direction, the second direction being perpendicular to the first direction, the second channel structure is adjacent to the first channel structure in the third direction, a center of the first channel structure is spaced apart from a center of the one vertical structure by a first distance, and a center of the second channel structure is spaced apart from the center of the first channel structure by a second distance, the second distance being less than the first distance. 19. A data storage system, comprising:a semiconductor storage device; and a controller electrically connected to the semiconductor storage device, the controller configured to control the semiconductor storage device, wherein the semiconductor storage device includesa substrate; a stack structure on the substrate, the stack structure including an alternating stack of interlayer insulating layers and gate electrodes, alternately stacked in a direction perpendicular to an upper surface of the substrate; separation regions having a first width and extending through the stack structure, such that the separation regions are connected to the substrate and extend in a first direction; a plurality of channel structures extending through the stack structure; and a plurality of vertical structures extending through the stack structure, and wherein at least one vertical structure among the plurality of vertical structures has a second width greater than the first width and extends through at least one separation region of the separation regions. 20. The data storage system of claim 19 , whereinthe semiconductor storage device further includes a plurality of upper separation regions between the separation regions and extending through a portion of the stack structure, and each of the separation regions has the first width in a second direction, the second direction being perpendicular to the first direction, and each of the plurality of vertical structures has the second width in the second direction.
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