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Semiconductor devices and data storage systems including the same

專利號(hào)
US12096637B2
公開日期
2024-09-17
申請(qǐng)人
Samsung Electronics Co., Ltd.(KR Gyeonggi-do)
發(fā)明人
Kohji Kanamori; Shinhwan Kang; Jeehoon Han
IPC分類
H10B43/50; H10B41/10; H10B41/27; H10B41/41; H10B41/50; H10B43/10; H10B43/27; H10B43/40
技術(shù)領(lǐng)域
separation,channel,may,vs3,structures,structure,upper,vertical,vs2,insulating
地域: Suwon-si

摘要

A semiconductor device includes a substrate; a stack structure on the substrate and including an alternating stack of interlayer insulating layers and gate electrodes; first and second separation regions each extending through the stack structure and extending in a first direction; a first upper separation region between the first and second separation regions and extending through a portion of the stack structure; a plurality of channel structures between the first and second separation regions and extending through the stack structure; and a plurality of first vertical structures each extending through a particular one of the first and second separation regions. Each of the first and second separation regions has a first width in a second direction that is perpendicular to the first direction. Each first vertical structure has a second width in the second direction, the second width being greater than the first width.

說明書

The channel structure CH may have a form in which the lower channel structures CHL of the lower stack structure GS1 and the upper channel structures CHU of the upper stack structure GS2 are connected, and may have a bent portion due to a difference in width in a region in which the connection is performed. A channel layer 140 and a channel embedded insulating layer 150 may be connected to each other between each of the lower channel structures CHL and each of the upper channel structures CHU. A channel pad 155 may be disposed only on each of the upper channel structures CHU. In some example embodiments, the lower channel structure CHL and the upper channel structure CHU may include the channel pad 155, respectively. In this case, the channel pad 155 of each of the lower channel structure CHL may be connected to the channel layer 140 of each of the upper channel structure CHU. An upper interlayer insulating layer 125 having a relatively thick thickness may be disposed in an uppermost portion of the lower stack structure GS1. Shapes of interlayer insulating layers 120 and a shape of the upper interlayer insulating layer 125 may be variously changed in some example embodiments.

Vertical structures VS are illustrated in a form connected without a difference in width in a region in which the lower stack structure GS1 and the upper stack structure GS2 are connected, but the present inventive concepts is not limited thereto. In some example embodiments, similarly to the channel structure CH, the vertical structures VS may have a bent portion due to a difference in width.

For other configurations, the description described above with reference to FIGS. 1 to 3 may be equally applied.

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