Optionally, the first DCI and the second DCI are sent in a same control resource set (CORESET).

Optionally, the first DCI and the second DCI are sent on a candidate control channel resource in a same search space set.

The sending module 720 may be implemented by a transceiver. The processing module 730 may be implemented by a processor. For specific functions and beneficial effects of the sending module 720 and the processing module 730, refer to the method shown in FIG. 5. Details are not described herein again.

FIG. 8 is a schematic diagram of a structure of a terminal device according to another embodiment of this application. As shown in FIG. 8, the terminal device 800 may include a transceiver 810, a processor 820, and a memory 830.

FIG. 8 shows only one memory and one processor. In an actual terminal device product, there may be one or more processors and one or more memories. The memory may also be referred to as a storage medium, a storage device, or the like. The memory may be disposed independent of the processor, or may be integrated with the processor. This is not limited in this embodiment of this application.

The transceiver 810, the processor 820, and the memory 830 communicate with each other through an internal connection path and transfer a control signal and/or a data signal.