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Signal transmission method, terminal device, and network device

專利號
US12108338B2
公開日期
2024-10-01
申請人
HUAWEI TECHNOLOGIES CO., LTD.(CN Shenzhen)
發(fā)明人
Lixia Xue; Zheng Chen
IPC分類
H04W52/02; H04W72/23
技術領域
dci,terminal,device,in,saving,first,drx,second,wus,network
地域: Guangdong

摘要

The present disclosure discloses an example signal transmission method and an example terminal device. One example signal transmission method includes monitoring, by a terminal device and based on a size of first downlink control information (DCI), the first DCI and second DCI that are sent by a network device, where the first DCI is carried on a power saving signal shared by a plurality of terminal devices including the terminal device, and the second DCI is carried on a terminal device specific power saving signal. It is determined by the terminal device and based on at least one of the first DCI or the second DCI, whether to monitor a data channel in a first time period.

說明書

The processor in the embodiments of this application may be an integrated circuit chip, and has a signal processing capability. In an implementation process, steps in the foregoing method may be implemented by using a hardware integrated logic circuit in the processor or by using instructions in a form of software. The processor in the embodiments of this application may be a general purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or another programmable logic device, a discrete gate or transistor logic device, or a discrete hardware component. The methods, the steps, and logic block diagrams that are disclosed in the embodiments of this application may be implemented or performed. The general purpose processor may be a microprocessor, or the processor may be any conventional processor or the like. The steps of the methods disclosed with reference to the embodiments of this application may be directly presented as being performed and completed by a hardware decoding processor, or performed and completed by a combination of hardware and a software module in a decoding processor. The software module may be located in a mature storage medium in the art, such as a random access memory (RAM), a flash memory, a read-only memory (ROM), a programmable read-only memory, an electrically erasable programmable memory, or a register. The storage medium is located in the memory, and the processor reads instructions in the memory and completes the steps in the foregoing methods in combination with hardware of the processor.

權利要求

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