The first wireless device 100 may include one or more processors 102 and one or more memories 104, and further include one or more transceivers 106 and/or one or more antennas 108. The processor(s) 102 may control the memory(s) 104 and/or the transceiver(s) 106 and may be configured to implement the descriptions, functions, procedures, proposals, methods, and/or operation flowcharts disclosed in this document. For example, the processor(s) 102 may process information in the memory(s) 104 to generate first information/signals and then transmit wireless signals including the first information/signals through the transceiver(s) 106. The processor(s) 102 may receive wireless signals including second information/signals through the transceiver(s) 106 and then store information obtained by processing the second information/signals in the memory(s) 104. The memory(s) 104 may be connected to the processor(s) 102 and may store various pieces of information related to operations of the processor(s) 102. For example, the memory(s) 104 may store software code including instructions for performing all or a part of processes controlled by the processor(s) 102 or for performing the descriptions, functions, procedures, proposals, methods, and/or operation flowcharts disclosed in this document. The processor(s) 102 and the memory(s) 104 may be a part of a communication modem/circuit/chip designed to implement RAT (e.g., LTE or NR). The transceiver(s) 106 may be connected to the processor(s) 102 and transmit and/or receive wireless signals through the one or more antennas 108. Each of the transceiver(s) 106 may include a transmitter and/or a receiver. The transceiver(s) 106 may be interchangeably used with radio frequency (RF) unit(s). In the present disclosure, the wireless device may be a communication modem/circuit/chip.