The second wireless device 200 may include one or more processors 202 and one or more memories 204, and further include one or more transceivers 206 and/or one or more antennas 208. The processor(s) 202 may control the memory(s) 204 and/or the transceiver(s) 206 and may be configured to implement the descriptions, functions, procedures, proposals, methods, and/or operation flowcharts disclosed in this document. For example, the processor(s) 202 may process information in the memory(s) 204 to generate third information/signals and then transmit wireless signals including the third information/signals through the transceiver(s) 206. The processor(s) 202 may receive wireless signals including fourth information/signals through the transceiver(s) 106 and then store information obtained by processing the fourth information/signals in the memory(s) 204. The memory(s) 204 may be connected to the processor(s) 202 and store various pieces of information related to operations of the processor(s) 202. For example, the memory(s) 204 may store software code including instructions for performing all or a part of processes controlled by the processor(s) 202 or for performing the descriptions, functions, procedures, proposals, methods, and/or operation flowcharts disclosed in this document. The processor(s) 202 and the memory(s) 204 may be a part of a communication modem/circuit/chip designed to implement RAT (e.g., LTE or NR). The transceiver(s) 206 may be connected to the processor(s) 202 and transmit and/or receive wireless signals through the one or more antennas 208. Each of the transceiver(s) 206 may include a transmitter and/or a receiver. The transceiver(s) 206 may be interchangeably used with RF unit(s). In the present disclosure, the wireless device may be a communication modem/circuit/chip.