Semiconductor storage device and forming method thereof
地域：
Hefei
摘要
The disclosure relates to a semiconductor storage device and a forming method thereof. The semiconductor storage device includes a substrate; a plurality of active region structures provided on the substrate; a shallow trench isolation structure provided within the substrate, the shallow trench isolation structure surround the plurality of active region structures; a plurality of conductive line structures, extending parallel to each other along a first direction, the conductive line structure include a first region and a second region, the first region being located over each of the plurality of active region structures, the second region is located over the shallow trench isolation structure; in a direction perpendicular to the substrate, the depth of the first region is greater than the depth of the second region.
說明書
This application is a continuation of International Application No. PCT/CN2021/112209 filed on Aug. 12, 2021, the entire contents of which are incorporated herein by reference.
The disclosure claims priority to Chinese Patent Application No. 202110894701.4, filed on Aug. 5, 2021 and entitled “Semiconductor Storage Device and Forming Method thereof”, the disclosure of which is hereby incorporated by reference in its entirety.
The disclosure relates to the field of semiconductor technology, and particularly to a semiconductor storage device and a forming method thereof.
With the development of Dynamic Random Access Memory (DRAM) preparation, in order to enable a DRAM to have a higher density, sizes of various storage units in the DRAM are reduced, a buried Word Line (WL) structure is typically used.
However, there are still some problems in existing trench gates. When the size of a memory continues to minimally shrink, the buried WL cuts a passing gate region between two active regions, and when reading and writing are repeated, accumulated parasitic electrons are generated in the active regions on both sides. When the parasitic electron flows to a source/drain that is electrically connected to a bit line through a bottom of the other buried WL adjacent to this row of buried WL, it will lead to reading and writing errors of the column bit line data. This phenomenon is called row hammer effect.
Embodiments of the disclosure provide a semiconductor storage device and a forming method thereof.
權(quán)利要求
What claimed is:1. A semiconductor storage device, comprising:a substrate; a plurality of active region structures provided on the substrate; a shallow trench isolation structure provided within the substrate, the shallow trench isolation structure surrounding the plurality of active region structures; a plurality of conductive line structures extending parallel to each other along a first direction, each of the plurality of conductive line structures comprising a first region and a second region, the first region being located over each of the plurality of active region structures, the second region being located over the shallow trench isolation structure in a direction perpendicular to the substrate, a depth of the first region being greater than a depth of the second region; and, wherein the first region of the each of the plurality of conductive line structures further comprises a gate structure, located at a bottom of the first region of the each of the plurality of conductive line structures, the gate structure comprise a barrier layer and a first sub-conductive layer, the barrier layer is located at a portion of sidewalls and a bottom surface of the bottom of the first region of the each of the plurality of conductive line structures, the first sub-conductive layer is provided at the inner-side of the barrier layer; wherein the first region of the each of the plurality of conductive line structures further comprises insulating sidewall and a second sub-conductive layer, the insulating sidewall is located at a portion of sidewalls over the bottom barrier layer of the first region, the second sub-conductive layer being provided at the inner-side of the insulating sidewall, the insulating sidewall is provided around the second sub-conductive layer. 2. The semiconductor storage device according to claim 1 , wherein the first region of the each of the plurality of conductive line structures further comprises a third sub-conductive layer, the third sub-conductive layer overlies the insulating sidewall and the second sub-conductive layer, and is connected to the second region of each of the plurality of conductive line structures. 3. The semiconductor storage device according to claim 2 , wherein the semiconductor storage device further comprises a capping layer, the capping layer is filled inside the second region and overlies the third sub-conductive layer. 4. The semiconductor storage device according to claim 1 , wherein a depth of the first region is ? to ? of a depth of the second region. 5. The semiconductor storage device according to claim 1 , wherein the barrier layer comprises a metal nitride. 6. The semiconductor storage device according to claim 2 , wherein a material of the first sub-conductive layer, a material of the second sub-conductive layer and a material of the third sub-conductive layer are same. 7. The semiconductor storage device according to claim 2 , wherein a thickness of the barrier layer is greater than a thickness of the insulating sidewall. 8. The semiconductor storage device according to claim 2 , wherein the third sub-conductive layer is provided with an adhesion layer thereon, the adhesion layer comprise a titanium nitride. 9. A method for forming a semiconductor storage device, wherein the semiconductor storage device comprises:a substrate; a plurality of active region structures provided on the substrate; a shallow trench isolation structure provided within the substrate, the shallow trench isolation structure surrounding the plurality of active region structures; and a plurality of conductive line structures extending parallel to each other along a first direction, each of the plurality of conductive line structures comprising a first region and a second region, the first region being located over each of the plurality of active region structures, the second region being located over the shallow trench isolation structure in a direction perpendicular to the substrate, a depth of the first region being greater than a depth of the second region; and, wherein the first region of the each of the plurality of conductive line structures further comprises a gate structure, located at a bottom of the first region of the each of the plurality of conductive line structures, the gate structure comprise a barrier layer and a first sub-conductive layer, the barrier layer is located at a portion of sidewalls and a bottom surface of the bottom of the first region of the each of the plurality of conductive line structures, the first sub-conductive layer is provided at the inner-side of the barrier layer; wherein the first region of the each of the plurality of conductive line structures further comprises insulating sidewall and a second sub-conductive layer, the insulating sidewall is located at a portion of sidewalls over the bottom barrier layer of the first region, the second sub-conductive layer being provided at the inner-side of the insulating sidewall, the insulating sidewall is provided around the second sub-conductive layer; and wherein the method comprises: providing the substrate; forming the plurality of active region structures and the shallow trench isolation structure on the substrate, the shallow trench isolation structure surrounding the plurality of active region structures; etching the plurality of active region structures and the shallow trench isolation structure for the first time to form a plurality of conductive line trenches that extend parallel to each other along the first direction, in the etching for the first time, a etching rate of the plurality of active region structures being greater than a etching rate of the shallow trench isolation structure; forming the plurality of conductive line structures in the plurality of conductive line trenches, each of the plurality of conductive line structures comprising the first region and the second region, the first region being located over each of the plurality of active region structures, the second region being located over the shallow trench isolation structure; a depth of the first region being greater than a depth of the second region; and, wherein forming the conductive line structure in the plurality of conductive line trenches comprises: depositing to form the barrier layer on a sidewall of the each of the plurality of conductive line structures; depositing to form the first sub-conductive layer within the barrier layer; etching back the barrier layer and the first sub-conductive layer, remaining portions of the barrier layer and the first sub-conductive layer located at the bottom of the first region to form the gate structure, wherein the barrier layer is located at the portion of sidewalls and the bottom surface of the bottom of the first region of the each of the plurality of conductive line structures, the first sub-conductive layer is provided at the inner-side of the barrier layer; wherein the etching for the first time comprises: forming a plurality of first mask structures along the first direction over the plurality of active region structures and the shallow trench isolation structure; etching the plurality of active region structures and the shallow trench isolation structure according to the plurality of first mask structures, a width of the first mask structure being a first width; and, wherein forming the plurality of conductive line structures in the plurality of conductive line trenches comprises: depositing an insulating material after the gate structure is formed; etching back the insulating material to fill a trench over the gate structure; forming a plurality of second mask structures along the first direction over the insulating material, a width of each of the plurality of second mask structures being a second width, the second width being less than the first width; etching the insulating material according to the plurality of second mask structures to form insulating sidewall over the barrier layer of the first region; and filling the second sub-conductive layer at the innerside of the insulating sidewall, wherein the second sub-conductive layer is provided at the innerside of the insulating sidewall. 10. The method according to claim 9 , wherein forming the plurality of conductive line structures in the plurality of conductive line trenches further comprises:depositing a fourth sub-conductive layer on the insulating sidewall and the second sub-conductive layer, the fourth sub-conductive layer filling each of the plurality of conductive line trenches. 11. The method according to claim 10 , wherein forming the plurality of conductive line structures in the plurality of conductive line trenches further comprises:forming a plurality of third mask structures along the first direction over a plurality of the fourth sub-conductive layers, a width of each of the plurality of third mask structures being less than the second width; etching the plurality of the fourth conductive layer according to the plurality of third mask structures to form a plurality of third sub-conductive layers, a width of each of the plurality of third sub-conductive layers is less than or equal to a width of each of the plurality of third mask structures. 12. The method according to claim 11 , further comprising:after forming the plurality of conductive line structures in the plurality of conductive line trenches, depositing to form a capping layer on the plurality of active region structures, the shallow trench isolation structure and the plurality of third sub-conductive layers. 13. The method according to claim 9 , wherein a depth of the first region is ? to ? of a depth of the second region. 14. The method according to claim 9 , wherein the barrier layer comprises a metal nitride. 15. The method according to claim 11 , wherein a material of the first sub-conductive layer, a material of the second sub-conductive layer and a material of the plurality of third sub-conductive layers are same.
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