Memory devices with dual encapsulation layers and methods of fabrication
地域：
CA
CA San Francisco
摘要
An integration process including an etch stop layer for high density memory and logic applications and methods of fabrication are described. While various examples are described with reference to FeRAM, capacitive structures formed herein can be used for any application where a capacitor is desired. For instance, the capacitive structure can be used for fabricating ferroelectric based or paraelectric based majority gate, minority gate, and/or threshold gate.
說(shuō)明書
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This application is a continuation of U.S. patent application Ser. No. 17/449,750 titled “AN ETCH STOP LAYER BASED INTEGRATION PROCESS FOR EMBEDDED MEMORY,” filed Oct. 1, 2021, and which is incorporated by reference in its entirety.
Integration of random-access memory (RAM) devices including (ferroelectric or paraelectric materials) on a same plane as interconnects of logic devices can be challenging. RAM devices include materials that have a variety of thicknesses and are difficult to etch. Targeting a device thickness in a memory region with a height constraint of interconnects in an adjacent logic region is challenging. As such alternate methods to pattern and form devices and alternative enabling integration methods essential for realizing a high-density memory array including ferroelectric and paraelectric materials are desirable.
權(quán)利要求
What is claimed is:1. A method of fabricating a device structure, the method comprising:forming a first conductive interconnect adjacent to a dielectric in a memory region and a second conductive interconnect adjacent to the dielectric in a logic region; depositing an etch stop layer on the dielectric and on the first conductive interconnect and on the second conductive interconnect; forming an electrode structure on the first conductive interconnect by etching a first opening in the etch stop layer and depositing a first conductive material; forming a memory device on the electrode structure, wherein forming the memory device comprises:depositing a material layer stack comprising a ferroelectric material or a paraelectric material on the electrode structure; and etching the material layer stack to form a first recessed surface in the etch stop layer in the memory region and in the logic region; forming a spacer on a first sidewall of the memory device by depositing a first encapsulation layer and etching the first encapsulation layer, wherein etching the first encapsulation layer substantially removes the first encapsulation layer adjacent to the spacer and from the logic region, and wherein etching the first encapsulation layer further comprises forming a second sidewall and a second recessed surface in the etch stop layer, wherein the second sidewall is substantially aligned with an outer sidewall of the spacer; depositing a second encapsulation layer on the memory device, on the spacer in the memory region and in the logic region, wherein depositing the second encapsulation layer comprises depositing on the second sidewall and on a portion of the second recessed surface; depositing a dielectric layer on the second encapsulation layer; forming a via electrode on the memory device by forming a second opening in the dielectric layer and in the second encapsulation layer and depositing a second conductive material in the second opening; and simultaneously forming a via structure on the second conductive interconnect and a metal line on the via structure by patterning a third opening in the dielectric and in the second encapsulation layer. 2. The method of claim 1 , wherein forming the electrode structure comprises forming the first opening having a greater lateral thickness than a lateral thickness of the first conductive interconnect. 3. The method of claim 1 , wherein etching the memory device comprises forming a mask on the material layer stack, and wherein the mask comprises a larger lateral width than a lateral width of the electrode structure. 4. The method of claim 1 , wherein etching the material layer stack further comprises forming a third sidewall in the etch stop layer that is substantially aligned with the first sidewall of the memory device. 5. The method of claim 1 , wherein etching the first encapsulation layer further comprises exposing an uppermost surface of the second conductive interconnect. 6. The method of claim 1 , wherein patterning the second opening comprises:forming a hanging trench in the dielectric layer; and masking a portion of the hanging trench and etching the dielectric layer and the second encapsulation layer to form a via opening that exposes the second conductive interconnect, wherein the via opening has a width that is less than a width of the hanging trench. 7. The method of claim 6 , wherein the via opening comprises a width that is between 25%-75% of a width of the hanging trench. 8. The method of claim 6 further comprises depositing a third conductive material in the third opening to simultaneously form the via structure on the second conductive interconnect and the metal line on the via structure. 9. The method of claim 1 , wherein the electrode structure is wider than the first conductive interconnect, and wherein etching the first opening in the etch stop layer comprises recessing a portion of the dielectric adjacent to the first conductive interconnect and depositing the first conductive material on a second sidewall of the first conductive interconnect. 10. The method of claim 1 , wherein the second recessed surface is below the first recessed surface by 1 nm to 3 nm. 11. The method of claim 10 , wherein depositing the first encapsulation layer comprises depositing one of: silicon, nitrogen, carbon, or aluminum and one or more of nitrogen or oxygen, and wherein depositing the second encapsulation layer comprises depositing silicon and one or more of oxygen, nitrogen, carbon, or aluminum, and wherein the second encapsulation layer is deposited to a thickness of less than 5 nm. 12. A method of fabricating a device structure, the method comprising:forming a first conductive interconnect in a dielectric in a memory region and a second conductive interconnect in a logic region; depositing an etch stop layer on the dielectric and on the first conductive interconnect and on the second conductive interconnect; forming an electrode structure on the first conductive interconnect by etching a first opening in the etch stop layer and depositing a first conductive material in the first opening; forming a memory device by depositing a material layer stack comprising a ferroelectric material or a paraelectric material on the electrode structure and etching the material layer stack, wherein etching the material layer stack forms a recessed surface in the etch stop layer in the memory region and in the logic region; forming a spacer on a sidewall of the memory device by depositing a first encapsulation layer and etching the first encapsulation layer, wherein etching the first encapsulation layer substantially removes the first encapsulation layer adjacent to the spacer and from the logic region; forming a second encapsulation layer on the memory device, on the spacer, on the dielectric in the memory region and in the logic region; depositing a dielectric layer on the second encapsulation layer; forming a hanging trench in the dielectric layer over the second conductive interconnect by etching the dielectric layer and simultaneously forming a second opening to expose the memory device, wherein the second opening is formed by sequentially etching the dielectric layer and etching the second encapsulation layer; forming a mask within the hanging trench and in the second opening, the mask comprising a third opening within the hanging trench; forming a fourth opening by etching the dielectric exposed by the third opening and by etching the second encapsulation layer after etching the dielectric, wherein etching the dielectric exposes the second conductive interconnect; removing the mask and simultaneously depositing a conductive material in the second opening, in the fourth opening, in the hanging trench, and on the second conductive interconnect; and planarizing the conductive material to simultaneously form a via electrode on the memory device, a via interconnect on the second conductive interconnect and a metal line on the via interconnect. 13. The method of claim 12 , wherein etching the dielectric layer to form the first opening comprises:halting the etching after the second encapsulation layer is exposed in the memory region; and continuing the etching to remove the second encapsulation layer from above the memory device. 14. The method of claim 12 , wherein prior to etching the second encapsulation layer, etching the dielectric layer further comprises over etching to expose the second encapsulation layer, and wherein etching to expose the second encapsulation layer recesses the hanging trench below a level of an uppermost surface of the memory device. 15. The method of claim 14 , wherein etching the second encapsulation layer to form the first opening recesses the hanging trench below the level of the uppermost surface of the memory device. 16. A method of fabricating a device structure, the method comprising:forming a first conductive interconnect in a dielectric in a memory region and a second conductive interconnect in a logic region; depositing an etch stop layer on the dielectric and on the first conductive interconnect and on the second conductive interconnect; forming an electrode structure on the first conductive interconnect by etching a first opening in the etch stop layer and depositing a first conductive material in the first opening; forming a memory device by depositing a material layer stack comprising a ferroelectric material or a paraelectric material on the electrode structure and etching the material layer stack, wherein etching the material layer stack forms a recessed surface in the etch stop layer in the memory region and in the logic region; forming a spacer on a sidewall of the memory device by depositing a first encapsulation layer and etching the first encapsulation layer, wherein etching substantially removes the first encapsulation layer adjacent to the spacer and from the logic region; forming a second encapsulation layer on the memory device, on the spacer, on the dielectric in the memory region and in the logic region; depositing a first dielectric layer on the second encapsulation layer; forming an intermediate electrode on the memory device by forming a second opening in the first dielectric layer and depositing a second conductive material in the second opening; forming a via structure on the second conductive interconnect by forming a third opening in the first dielectric layer and in the second encapsulation layer and depositing a third conductive material in the third opening; depositing a second dielectric layer on the first dielectric layer and on the intermediate electrode and on the via structure; simultaneously forming a fourth opening and a fifth opening in the second dielectric layer, wherein the fourth opening exposes the intermediate electrode, and the fifth opening exposes the via structure; and depositing a fourth conductive material in the fourth opening and in the fifth opening to form a via electrode on the intermediate electrode and a metal line on the via structure. 17. The method of claim 16 , wherein the intermediate electrode is formed prior to forming the via structure. 18. The method of claim 16 , wherein the via structure is formed prior to forming the intermediate electrode. 19. The method of claim 16 , wherein after depositing the second dielectric layer a planarization process is performed to define a vertical thickness of the via structure to be formed, wherein the memory device has a vertical thickness that is between 30-80% of a vertical thickness of the via structure, and wherein the vertical thickness of the second dielectric layer and the second encapsulation layer is between 20%-70% of the via structure. 20. The method of claim 16 , wherein, the second encapsulation layer is deposited to a thickness between 5 nm and 20 nm.
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