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Memory devices with dual encapsulation layers and methods of fabrication

專(zhuān)利號(hào)
US12108608B1
公開(kāi)日期
2024-10-01
申請(qǐng)人
Kepler Computing Inc.（US CA San Francisco）
發(fā)明人
Noriyuki Sato; Debraj Guhabiswas; Tanay Gosavi; Niloy Mukherjee; Amrita Mathuriya; Sasikanth Manipatruni
IPC分類(lèi)
H10B53/30; H01L49/02
技術(shù)領(lǐng)域
etch,electrode,in,conductive,memory,layer,sidewall,dielectric,device,structure
地域： CA CA San Francisco

摘要

An integration process including an etch stop layer for high density memory and logic applications and methods of fabrication are described. While various examples are described with reference to FeRAM, capacitive structures formed herein can be used for any application where a capacitor is desired. For instance, the capacitive structure can be used for fabricating ferroelectric based or paraelectric based majority gate, minority gate, and/or threshold gate.

說(shuō)明書(shū)

Example 21: The device of example 16, wherein the memory device comprises a paraelectric material which includes: SrTiO3, Ba(x)Sr(y)TiO3 (where x is ?0.05, and y is 0.95), HfZrO2, Hf—Si—O, La-substituted PbTiO3, or a PMN-PT based relaxor ferroelectrics.

Example 1a: A method of fabricating a device structure, the method comprising: forming a first conductive interconnect in a dielectric in a memory region and a second conductive interconnect in a logic region; depositing an etch stop layer on the dielectric and on the first conductive interconnect and on the second conductive interconnect; forming an electrode structure on the first conductive interconnect by etching an opening in the etch stop layer and depositing a first conductive material; forming a memory device by depositing a material layer stack comprising a ferroelectric material or a paraelectric material on the electrode structure and etching the material layer stack; forming a spacer on a sidewall of the memory device by depositing an encapsulation layer and etching the encapsulation layer; depositing a dielectric layer on the memory device; forming a via electrode on the memory device by forming a first opening in the dielectric layer and depositing a second conductive material in the first opening; and forming a via structure on the second conductive interconnect and a metal line on the via structure by patterning a second opening in the dielectric and in the etch stop layer.

Example 2a: The method of example 1a, wherein depositing the material layer stack comprises depositing at least two layers comprising the ferroelectric material.

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