Memory devices with dual encapsulation layers and methods of fabrication
摘要
說明書
Example 2b: The device of example 1b, wherein the memory device comprises: a first conductive layer comprising a non-Pb based perovskite metal oxide, the first conductive layer comprising a first sidewall having a first slope; a ferroelectric dielectric layer comprising a non-Pb based perovskite material on the first conductive layer, the ferroelectric dielectric layer comprising a second sidewall having a second slope; and a second conductive layer comprising non-Pb based perovskite metal oxide on the ferroelectric dielectric layer, the second conductive layer comprising a third sidewall having a third slope, wherein the first slope, the second slope and the third slope are substantially close to ninety degrees relative to a lowermost surface of the memory device.
Example 3b: The device of example 1b, wherein the electrode structure comprises a cylindrical shape, and the first conductive interconnect comprises a cylindrical shape, wherein the first lateral thickness is a first diameter, and the second lateral thickness is a second diameter, and the third lateral thickness is a third diameter, wherein the third diameter is greater than the first diameter and the second diameter.
Example 4b: The device of example 3b, wherein a first vertical axis of the electrode structure is offset from a second vertical axis of the first conductive interconnect.
Example 5b: The device of example 4b, wherein a third vertical axis of the memory device is offset from the first vertical axis of the electrode structure.
Example 6b: The device of example 1b, wherein a sum of the first vertical thickness and the second vertical thickness is substantially equal to the fourth vertical thickness, and wherein the third vertical thickness is substantially equal to the fifth vertical thickness.
