Memory devices with dual encapsulation layers and methods of fabrication
地域：
CA
CA San Francisco
摘要
An integration process including an etch stop layer for high density memory and logic applications and methods of fabrication are described. While various examples are described with reference to FeRAM, capacitive structures formed herein can be used for any application where a capacitor is desired. For instance, the capacitive structure can be used for fabricating ferroelectric based or paraelectric based majority gate, minority gate, and/or threshold gate.
說明書
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Example 12b: The device of example 1b, wherein the etch stop layer has a sixth vertical thickness under the memory device and a seventh vertical thickness adjacent to the via structure, wherein the sixth vertical thickness is greater than the seventh vertical thickness.
Example 13b: The device of example 12b, wherein the first vertical thickness is at least two times greater than the second vertical thickness.
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