Memory devices with dual encapsulation layers and methods of fabrication
地域：
CA
CA San Francisco
摘要
An integration process including an etch stop layer for high density memory and logic applications and methods of fabrication are described. While various examples are described with reference to FeRAM, capacitive structures formed herein can be used for any application where a capacitor is desired. For instance, the capacitive structure can be used for fabricating ferroelectric based or paraelectric based majority gate, minority gate, and/or threshold gate.
說(shuō)明書
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Example 15b: The device of example 14b, wherein the first vertical thickness is greater than the second vertical thickness by at least 2 nm.
Example 16b: The device of example 14b, wherein the spacer comprises a sixth sidewall opposite to the fifth sidewall, wherein the sixth sidewall is substantially aligned with the fourth sidewall.
Example 17b: The device of example 14b, wherein the via electrode is adjacent to a portion of the encapsulation layer on the memory device.
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