Memory devices with dual encapsulation layers and methods of fabrication
摘要
說(shuō)明書(shū)
To prevent degradation of layers in the memory device 108 during a fabrication process, a spacer 114 may be present on sidewalls and on top surfaces of memory device 108. In the illustrative embodiment, spacer 114 is sidewalls 108A of memory device 108 but not on a top surface 108B. Spacer 114 also provides a hermetic seal to sensitive layers within memory device 108. When WES is greater than WMD, as is shown, spacer 114 may be on a portion of the electrode structure 112. In some embodiments, depending on a lateral thickness, TEC, spacer 114 may be fully on the electrode structure 112 or partially on each of electrode structure 112 and the etch stop layer 113. In the illustrative embodiment, spacer 114 is on electrode structure 112. In some embodiments, when WES is equal to a sum of WMD and WEC, then an outermost sidewall surface 114A of the spacer 114 is substantially aligned with sidewall 112A of the electrode structure 112. In the illustrative embodiment, the spacer 114 has a curved uppermost portion and outermost sidewall surface 114A. In some embodiments, outermost sidewall surface 114A matches a contour of sidewall 108A.
該功能需要專(zhuān)業(yè)版企業(yè)版VIP權(quán)限，您可以：
掃描加專(zhuān)利匯官方微信交流群
