Memory devices with dual encapsulation layers and methods of fabrication
地域：
CA
CA San Francisco
摘要
An integration process including an etch stop layer for high density memory and logic applications and methods of fabrication are described. While various examples are described with reference to FeRAM, capacitive structures formed herein can be used for any application where a capacitor is desired. For instance, the capacitive structure can be used for fabricating ferroelectric based or paraelectric based majority gate, minority gate, and/or threshold gate.
說明書
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The deposition process is continued with a deposition of conductive layer 800° C. on dielectric layer 800B. In an exemplary embodiment, the conductive layer 800° C. includes a material that is the same or substantially the same as the material of conductive layer 800A. When conductive layers 800A and 800° C. include the same material, the material layer stack is symmetric. In different embodiments, conductive layer 800° C. can have a different thickness than conductive layer 800A. In embodiments, conductive layer 800° C. is deposited to a thickness, T3, between 3 nm and 30 nm. Conductive layer 800° C. between 3 nm and 30 nm can facilitate the patterning process.
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